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Merge branch '86Box:master' into HDD_Model_Batch

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MaxwellS04 2024-12-18 08:06:51 +07:00 committed by GitHub
commit 172bef24f7
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7 changed files with 84 additions and 41 deletions
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2
src/include/86box/machine.h
View file

@ -722,7 +722,7 @@ extern int machine_at_pb680_init(const machine_t *);
extern int machine_at_pb810_init(const machine_t *);
extern int machine_at_mb520n_init(const machine_t *);
extern int machine_at_i430vx_init(const machine_t *);
extern int machine_at_hitman_init(const machine_t *);
extern int machine_at_gw2kte_init(const machine_t *);
extern int machine_at_ma23c_init(const machine_t *);
extern int machine_at_nupro592_init(const machine_t *);

2
src/include/86box/mem.h
View file

@ -179,6 +179,7 @@ typedef struct _mem_mapping_ {
uint32_t base;
uint32_t size;
uint32_t base_ignore;
uint32_t mask;
uint8_t (*read_b)(uint32_t addr, void *priv);
@ -400,6 +401,7 @@ extern void mem_mapping_set_p(mem_mapping_t *, void *priv);
extern void mem_mapping_set_addr(mem_mapping_t *,
uint32_t base, uint32_t size);
extern void mem_mapping_set_base_ignore(mem_mapping_t *, uint32_t base_ignore);
extern void mem_mapping_set_exec(mem_mapping_t *, uint8_t *exec);
extern void mem_mapping_set_mask(mem_mapping_t *, uint32_t mask);
extern void mem_mapping_disable(mem_mapping_t *);

12
src/machine/m_at_socket7.c
View file

@ -825,15 +825,15 @@ machine_at_i430vx_init(const machine_t *model)
}
int
machine_at_hitman_init(const machine_t *model)
machine_at_gw2kte_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/hitman/1008CY1T.BIO",
"roms/machines/hitman/1008CY1T.BI1",
"roms/machines/hitman/1008CY1T.BI2",
"roms/machines/hitman/1008CY1T.BI3",
"roms/machines/hitman/1008CY1T.RCV",
ret = bios_load_linear_combined2("roms/machines/gw2kte/1008CY1T.BIO",
"roms/machines/gw2kte/1008CY1T.BI1",
"roms/machines/gw2kte/1008CY1T.BI2",
"roms/machines/gw2kte/1008CY1T.BI3",
"roms/machines/gw2kte/1008CY1T.RCV",
0x3a000, 128);
if (bios_only || !ret)

8
src/machine/machine_table.c
View file

@ -11953,16 +11953,14 @@ const machine_t machines[] = {
.snd_device = NULL,
.net_device = NULL
},
/* 430VX */
/* Has a SM(S)C FDC37C932FR Super I/O chip with on-chip KBC with AMI
MegaKey (revision '5') KBC firmware. */
{
.name = "[i430VX] Gateway 2000 Hitman",
.internal_name = "hitman",
.internal_name = "gw2kte",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_hitman_init,
.init = machine_at_gw2kte_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
@ -11996,8 +11994,6 @@ const machine_t machines[] = {
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{

72
src/mem/mem.c
View file

@ -2351,41 +2351,47 @@ mem_mapping_recalc(uint64_t base, uint64_t size)
/* In range? */
if (map->enable && (uint64_t) map->base < ((uint64_t) base + (uint64_t) size) &&
((uint64_t) map->base + (uint64_t) map->size) > (uint64_t) base) {
uint64_t i_a = (~map->base_ignore) + 0x00000001ULL;
uint64_t i_s = 0x00000000ULL;
uint64_t i_e = map->base_ignore;
uint64_t i_c = 0x00000000ULL;
uint64_t start = (map->base < base) ? map->base : base;
uint64_t end = (((uint64_t) map->base + (uint64_t) map->size) < (base + size)) ?
((uint64_t) map->base + (uint64_t) map->size) : (base + size);
if (start < map->base)
start = map->base;
for (c = start; c < end; c += MEM_GRANULARITY_SIZE) {
/* CPU */
n = !!in_smm;
wp = _mem_wp[c >> MEM_GRANULARITY_BITS];
for (i_c = i_s; i_c <= i_e; i_c += i_a) {
for (c = (start + i_c); c < (end + i_c); c += MEM_GRANULARITY_SIZE) {
/* CPU */
n = !!in_smm;
wp = _mem_wp[c >> MEM_GRANULARITY_BITS];
if (map->exec && mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].x))
_mem_exec[c >> MEM_GRANULARITY_BITS] = map->exec + (c - map->base);
if (!wp && (map->write_b || map->write_w || map->write_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
write_mapping[c >> MEM_GRANULARITY_BITS] = map;
if ((map->read_b || map->read_w || map->read_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
read_mapping[c >> MEM_GRANULARITY_BITS] = map;
if (map->exec && mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].x))
_mem_exec[c >> MEM_GRANULARITY_BITS] = map->exec + (c - map->base);
if (!wp && (map->write_b || map->write_w || map->write_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
write_mapping[c >> MEM_GRANULARITY_BITS] = map;
if ((map->read_b || map->read_w || map->read_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
read_mapping[c >> MEM_GRANULARITY_BITS] = map;
/* Bus */
n |= STATE_BUS;
wp = _mem_wp_bus[c >> MEM_GRANULARITY_BITS];
/* Bus */
n |= STATE_BUS;
wp = _mem_wp_bus[c >> MEM_GRANULARITY_BITS];
if (!wp && (map->write_b || map->write_w || map->write_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
write_mapping_bus[c >> MEM_GRANULARITY_BITS] = map;
if ((map->read_b || map->read_w || map->read_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
read_mapping_bus[c >> MEM_GRANULARITY_BITS] = map;
if (!wp && (map->write_b || map->write_w || map->write_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
write_mapping_bus[c >> MEM_GRANULARITY_BITS] = map;
if ((map->read_b || map->read_w || map->read_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
read_mapping_bus[c >> MEM_GRANULARITY_BITS] = map;
}
}
}
map = map->next;
@ -2597,6 +2603,20 @@ mem_mapping_set_addr(mem_mapping_t *map, uint32_t base, uint32_t size)
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_base_ignore(mem_mapping_t *map, uint32_t base_ignore)
{
/* Remove old mapping. */
map->enable = 0;
mem_mapping_recalc(map->base, map->size);
/* Set new mapping. */
map->enable = 1;
map->base_ignore = base_ignore;
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_exec(mem_mapping_t *map, uint8_t *exec)
{

26
src/network/net_pcnet.c
View file

@ -2481,36 +2481,58 @@ pcnet_readl(uint16_t addr, void *priv)
static void
pcnet_mmio_writeb(uint32_t addr, uint8_t val, void *priv)
{
if (!(addr & 0x10)) {
pcnet_aprom_writeb((nic_t *) priv, addr, val);
return;
}
pcnet_write((nic_t *) priv, addr, val, 1);
}
static void
pcnet_mmio_writew(uint32_t addr, uint16_t val, void *priv)
{
if (!(addr & 0x10)) {
pcnet_aprom_writeb((nic_t *) priv, addr, val);
pcnet_aprom_writeb((nic_t *) priv, addr + 1, val >> 8);
return;
}
pcnet_write((nic_t *) priv, addr, val, 2);
}
static void
pcnet_mmio_writel(uint32_t addr, uint32_t val, void *priv)
{
if (!(addr & 0x10)) {
pcnet_aprom_writeb((nic_t *) priv, addr, val);
pcnet_aprom_writeb((nic_t *) priv, addr + 1, val >> 8);
pcnet_aprom_writeb((nic_t *) priv, addr + 2, val >> 16);
pcnet_aprom_writeb((nic_t *) priv, addr + 3, val >> 24);
return;
}
pcnet_write((nic_t *) priv, addr, val, 4);
}
static uint8_t
pcnet_mmio_readb(uint32_t addr, void *priv)
{
if (!(addr & 0x10))
return pcnet_aprom_readb((nic_t *) priv, addr);
return (pcnet_read((nic_t *) priv, addr, 1));
}
static uint16_t
pcnet_mmio_readw(uint32_t addr, void *priv)
{
if (!(addr & 0x10))
return pcnet_aprom_readb((nic_t *) priv, addr) | (pcnet_aprom_readb((nic_t *) priv, addr + 1) << 8);
return (pcnet_read((nic_t *) priv, addr, 2));
}
static uint32_t
pcnet_mmio_readl(uint32_t addr, void *priv)
{
if (!(addr & 0x10))
return pcnet_aprom_readb((nic_t *) priv, addr) | (pcnet_aprom_readb((nic_t *) priv, addr + 1) << 8) | (pcnet_aprom_readb((nic_t *) priv, addr + 2) << 16) | (pcnet_aprom_readb((nic_t *) priv, addr + 3) << 24);
return (pcnet_read((nic_t *) priv, addr, 4));
}
@ -2607,7 +2629,7 @@ pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
/* Then let's set the PCI regs. */
pcnet_pci_bar[0].addr_regs[addr & 3] = val;
/* Then let's calculate the new I/O base. */
pcnet_pci_bar[0].addr &= 0xff00;
pcnet_pci_bar[0].addr &= 0xffe0;
dev->PCIBase = pcnet_pci_bar[0].addr;
/* Log the new base. */
pcnet_log(4, "%s: New I/O base is %04X\n", dev->name, dev->PCIBase);
@ -2685,7 +2707,7 @@ pcnet_pci_read(UNUSED(int func), int addr, void *priv)
case 0x0E:
return 0; /*Header type */
case 0x10:
return 1; /*I/O space*/
return pcnet_pci_bar[0].addr_regs[0] | 1; /*I/O space*/
case 0x11:
return pcnet_pci_bar[0].addr_regs[1];
case 0x12:

3
src/video/vid_cl54xx.c
View file

@ -4306,6 +4306,9 @@ gd54xx_init(const device_t *info)
mem_mapping_disable(&gd54xx->bios_rom.mapping);
}
if ((svga->crtc[0x27] <= CIRRUS_ID_CLGD5429) || (!gd54xx->pci && !gd54xx->vlb))
mem_mapping_set_base_ignore(&gd54xx->linear_mapping, 0xff000000);
mem_mapping_set_p(&svga->mapping, gd54xx);
mem_mapping_disable(&gd54xx->mmio_mapping);
mem_mapping_disable(&gd54xx->linear_mapping);