mirror of
https://github.com/86Box/86Box.git
synced 2025-01-22 09:11:50 -05:00
Merge branch 'master' of https://github.com/86Box/86Box
This commit is contained in:
OBattler
commit
4123fad19b
1 changed files with 128 additions and 41 deletions
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|
@ -15,12 +15,13 @@
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* Copyright 2021-2022 RichardG.
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*/
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||||
#include <math.h>
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||||
#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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||||
#include <stdlib.h>
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#include <string.h>
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||||
#include <wchar.h>
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||||
#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/dma.h>
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@ -51,6 +52,12 @@ enum {
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CRYSTAL_CS4237B = 0xc8,
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CRYSTAL_CS4238B = 0xc9
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};
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enum {
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CRYSTAL_RAM_CMD = 0,
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CRYSTAL_RAM_ADDR_LO = 1,
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CRYSTAL_RAM_ADDR_HI = 2,
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CRYSTAL_RAM_DATA = 3
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};
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enum {
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CRYSTAL_SLAM_NONE = 0,
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CRYSTAL_SLAM_INDEX = 1,
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@ -58,15 +65,31 @@ enum {
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CRYSTAL_SLAM_BYTE2 = 3
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};
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#ifdef ENABLE_CS423X_LOG
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int cs423x_do_log = ENABLE_CS423X_LOG;
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static void
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cs423x_log(const char *fmt, ...)
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{
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va_list ap;
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if (cs423x_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define cs423x_log(fmt, ...)
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#endif
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static const uint8_t slam_init_key[32] = { 0x96, 0x35, 0x9A, 0xCD, 0xE6, 0xF3, 0x79, 0xBC,
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0x5E, 0xAF, 0x57, 0x2B, 0x15, 0x8A, 0xC5, 0xE2,
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0xF1, 0xF8, 0x7C, 0x3E, 0x9F, 0x4F, 0x27, 0x13,
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0x09, 0x84, 0x42, 0xA1, 0xD0, 0x68, 0x34, 0x1A };
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static const uint8_t cs4236b_eeprom[8224] = {
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static const uint8_t cs4236b_default[] = {
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// clang-format off
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/* Chip configuration */
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0x55, 0xbb, /* magic */
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0x00, 0x00, /* length */
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0x00, 0x03, /* CD-ROM and modem decode */
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0x80, /* misc. config */
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0x80, /* global config */
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@ -77,8 +100,9 @@ static const uint8_t cs4236b_eeprom[8224] = {
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0x75, 0xb9, 0xfc, /* IRQ routing */
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0x10, 0x03, /* DMA routing */
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/* PnP resources */
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0x00
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/* Default PnP resources */
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/* TODO: broken, not picked up by VS440FX BIOS, pending hardware research of the actual defaults */
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0x0e, 0x63, 0x42, 0x36, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0a, 0x10, 0x00, 0x14, 0x41, 0xd0, 0xff, 0xff, 0x79, 0x00
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// clang-format on
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};
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@ -97,6 +121,7 @@ typedef struct cs423x_t {
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uint16_t ram_addr;
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uint16_t eeprom_size : 11;
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uint16_t pnp_offset;
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uint16_t pnp_size;
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uint8_t type;
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uint8_t ad1848_type;
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uint8_t regs[8];
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@ -130,6 +155,8 @@ cs423x_nvram(cs423x_t *dev, uint8_t save)
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else
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(void) !fread(dev->eeprom_data, sizeof(dev->eeprom_data), 1, fp);
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fclose(fp);
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} else {
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cs423x_log("CS423x: EEPROM data %s failed\n", save ? "save" : "load");
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}
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}
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@ -147,14 +174,24 @@ cs423x_read(uint16_t addr, void *priv)
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ret |= 0x04;
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break;
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case 3: /* Control Indirect Access Register */
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/* Intel VS440FX BIOS tells CS4236 from CS4232 through the upper bits. Setting them is enough. */
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ret |= 0xf0;
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break;
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case 4: /* Control Indirect Data Register */
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ret = dev->indirect_regs[dev->regs[3]];
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break;
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case 5: /* Control/RAM Access */
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/* Reading RAM is undocumented; the Windows drivers do so. */
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if (dev->ram_dl == 3)
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ret = dev->ram_data[dev->ram_addr++];
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/* Reading RAM is undocumented, but performed by:
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- Windows drivers (unknown purpose)
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- Intel VS440FX BIOS (PnP ROM checksum recalculation) */
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if (dev->ram_dl == CRYSTAL_RAM_DATA) {
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ret = dev->ram_data[dev->ram_addr];
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cs423x_log("CS423x: RAM read(%04X) = %02X\n", dev->ram_addr, ret);
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dev->ram_addr++;
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}
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break;
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case 7: /* Global Status */
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@ -175,6 +212,8 @@ cs423x_read(uint16_t addr, void *priv)
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break;
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}
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cs423x_log("CS423x: read(%X) = %02X\n", reg, ret);
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|
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return ret;
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}
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@ -182,7 +221,9 @@ static void
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cs423x_write(uint16_t addr, uint8_t val, void *priv)
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{
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cs423x_t *dev = (cs423x_t *) priv;
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uint8_t reg = addr & 0x07;
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uint8_t reg = addr & 7;
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cs423x_log("CS423x: write(%X, %02X)\n", reg, val);
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switch (reg) {
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case 1: /* EEPROM Interface */
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@ -248,7 +289,7 @@ cs423x_write(uint16_t addr, uint8_t val, void *priv)
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|
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case 5: /* Control/RAM Access */
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switch (dev->ram_dl) {
|
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case 0: /* commands */
|
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case CRYSTAL_RAM_CMD: /* commands */
|
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switch (val) {
|
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case 0x55: /* Disable PnP Key */
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dev->pnp_enable = 0;
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@ -266,7 +307,7 @@ cs423x_write(uint16_t addr, uint8_t val, void *priv)
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break;
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case 0xaa: /* Download RAM */
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dev->ram_dl = 1;
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dev->ram_dl = CRYSTAL_RAM_ADDR_LO;
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break;
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default:
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@ -274,17 +315,19 @@ cs423x_write(uint16_t addr, uint8_t val, void *priv)
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}
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break;
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case 1: /* low address byte */
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case CRYSTAL_RAM_ADDR_LO: /* low address byte */
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dev->ram_addr = val;
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dev->ram_dl++;
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dev->ram_dl = CRYSTAL_RAM_ADDR_HI;
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break;
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case 2: /* high address byte */
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dev->ram_addr |= (val << 8);
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dev->ram_dl++;
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case CRYSTAL_RAM_ADDR_HI: /* high address byte */
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dev->ram_addr |= val << 8;
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dev->ram_dl = CRYSTAL_RAM_DATA;
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cs423x_log("CS423x: RAM start(%04X)\n", dev->ram_addr);
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break;
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case 3: /* data */
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case CRYSTAL_RAM_DATA: /* data */
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cs423x_log("CS423x: RAM write(%04X, %02X)\n", dev->ram_addr, val);
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dev->ram_data[dev->ram_addr++] = val;
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break;
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|
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|
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@ -296,7 +339,8 @@ cs423x_write(uint16_t addr, uint8_t val, void *priv)
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case 6: /* RAM Access End */
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/* TriGem Delhi-III BIOS writes undocumented value 0x40 instead of 0x00. */
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if ((val == 0x00) || (val == 0x40)) {
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dev->ram_dl = 0;
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cs423x_log("CS423x: RAM end\n");
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dev->ram_dl = CRYSTAL_RAM_CMD;
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/* Update PnP state and resource data. */
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cs423x_pnp_enable(dev, 1, 0);
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@ -319,6 +363,9 @@ cs423x_slam_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
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cs423x_t *dev = (cs423x_t *) priv;
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uint8_t idx;
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if ((dev->slam_state != CRYSTAL_SLAM_NONE) || (val == slam_init_key[dev->key_pos])) /* cut down on ISAPnP-related noise */
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cs423x_log("CS423x: slam_write(%02X)\n", val);
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switch (dev->slam_state) {
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case CRYSTAL_SLAM_NONE:
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/* Not in SLAM: read and compare Crystal key. */
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@ -333,6 +380,7 @@ cs423x_slam_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
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}
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/* Enter SLAM. */
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cs423x_log("CS423x: SLAM unlocked\n");
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dev->slam_state = CRYSTAL_SLAM_INDEX;
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}
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} else {
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@ -343,6 +391,8 @@ cs423x_slam_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
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case CRYSTAL_SLAM_INDEX:
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/* Intercept the Activate Audio Device command. */
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if (val == 0x79) {
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cs423x_log("CS423x: Exiting SLAM\n");
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/* Apply the last logical device's configuration. */
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if (dev->slam_config) {
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cs423x_pnp_config_changed(dev->slam_ld, dev->slam_config, dev);
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@ -363,6 +413,7 @@ cs423x_slam_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
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case CRYSTAL_SLAM_BYTE1:
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case CRYSTAL_SLAM_BYTE2:
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/* Write register value: two bytes for I/O ports, single byte otherwise. */
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cs423x_log("CS423x: SLAM write(%02X, %02X)\n", dev->slam_reg, val);
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switch (dev->slam_reg) {
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case 0x06: /* Card Select Number */
|
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isapnp_set_csn(dev->pnp_card, val);
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|
|
@ -433,7 +484,7 @@ cs423x_slam_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
|
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break;
|
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}
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|
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/* Prepare for the next register, unless a two-byte read returns above. */
|
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/* Prepare for the next register, unless a two-byte write returns above. */
|
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dev->slam_state = CRYSTAL_SLAM_INDEX;
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break;
|
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|
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|
|
@ -454,8 +505,11 @@ cs423x_slam_enable(cs423x_t *dev, uint8_t enable)
|
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|
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/* Enable SLAM if the CKD bit is not set. */
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if (enable && !(dev->ram_data[0x4002] & 0x10)) {
|
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cs423x_log("CS423x: Enabling SLAM\n");
|
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dev->slam_enable = 1;
|
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io_sethandler(0x279, 1, NULL, NULL, NULL, cs423x_slam_write, NULL, NULL, dev);
|
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} else {
|
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cs423x_log("CS423x: Disabling SLAM\n");
|
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}
|
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}
|
||||
|
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|
|
@ -471,6 +525,7 @@ cs423x_ctxswitch_write(uint16_t addr, UNUSED(uint8_t val), void *priv)
|
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/* Flip context bit. */
|
||||
dev->regs[7] ^= 0x80;
|
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ctx ^= 0x80;
|
||||
cs423x_log("CS423x: Context switch to %s\n", ctx ? "WSS" : "SBPro");
|
||||
|
||||
/* Update CD audio filter.
|
||||
FIXME: not thread-safe: filter function TOCTTOU in sound_cd_thread! */
|
||||
|
|
@ -540,10 +595,12 @@ cs423x_get_music_buffer(int32_t *buffer, int len, void *priv)
|
|||
static void
|
||||
cs423x_pnp_enable(cs423x_t *dev, uint8_t update_rom, uint8_t update_hwconfig)
|
||||
{
|
||||
cs423x_log("CS423x: Updating PnP ROM=%d hwconfig=%d\n", update_rom, update_hwconfig);
|
||||
|
||||
if (dev->pnp_card) {
|
||||
/* Update PnP resource data if requested. */
|
||||
if (update_rom)
|
||||
isapnp_update_card_rom(dev->pnp_card, &dev->ram_data[dev->pnp_offset], 384);
|
||||
isapnp_update_card_rom(dev->pnp_card, &dev->ram_data[dev->pnp_offset], dev->pnp_size);
|
||||
|
||||
/* Disable PnP key if the PKD bit is set, or if it was disabled by command 0x55. */
|
||||
/* But wait! The TriGem Delhi-III BIOS sends command 0x55, and its behavior doesn't
|
||||
|
|
@ -697,9 +754,21 @@ cs423x_reset(void *priv)
|
|||
/* Clear RAM. */
|
||||
memset(dev->ram_data, 0, sizeof(dev->ram_data));
|
||||
|
||||
/* Load default configuration data to RAM. */
|
||||
memcpy(&dev->ram_data[0x4000], cs4236b_default, sizeof(cs4236b_default));
|
||||
dev->pnp_size = 19;
|
||||
|
||||
if (dev->eeprom) {
|
||||
/* Load EEPROM data to RAM. */
|
||||
memcpy(&dev->ram_data[0x4000], &dev->eeprom_data[4], MIN(384, ((dev->eeprom_data[2] << 8) | dev->eeprom_data[3]) - 4));
|
||||
/* Load EEPROM data to RAM if the magic bytes are present. */
|
||||
if ((dev->eeprom_data[0] == 0x55) && (dev->eeprom_data[1] == 0xbb)) {
|
||||
cs423x_log("CS423x: EEPROM data valid, loading to RAM\n");
|
||||
dev->pnp_size = (dev->eeprom_data[2] << 8) | dev->eeprom_data[3];
|
||||
if (dev->pnp_size > 384)
|
||||
dev->pnp_size = 384;
|
||||
memcpy(&dev->ram_data[0x4000], &dev->eeprom_data[4], sizeof(dev->eeprom_data) - 4);
|
||||
} else {
|
||||
cs423x_log("CS423x: EEPROM data invalid, ignoring\n");
|
||||
}
|
||||
|
||||
/* Save EEPROM contents to file. */
|
||||
cs423x_nvram(dev, 1);
|
||||
|
|
@ -734,6 +803,7 @@ cs423x_init(const device_t *info)
|
|||
|
||||
/* Initialize model-specific data. */
|
||||
dev->type = info->local & 0xff;
|
||||
cs423x_log("CS423x: init(%02X)\n", dev->type);
|
||||
switch (dev->type) {
|
||||
case CRYSTAL_CS4235:
|
||||
case CRYSTAL_CS4236B:
|
||||
|
|
@ -743,30 +813,41 @@ cs423x_init(const device_t *info)
|
|||
dev->ad1848_type = (dev->type == CRYSTAL_CS4235) ? AD1848_TYPE_CS4235 : AD1848_TYPE_CS4236;
|
||||
dev->pnp_offset = 0x4013;
|
||||
|
||||
/* Different Chip Version and ID registers, which shouldn't be reset by ad1848_init */
|
||||
/* Different Chip Version and ID registers, which shouldn't be reset by ad1848_init. */
|
||||
dev->ad1848.xregs[25] = dev->type;
|
||||
|
||||
if (!(info->local & CRYSTAL_NOEEPROM)) {
|
||||
/* Load EEPROM contents from template. */
|
||||
memcpy(dev->eeprom_data, cs4236b_eeprom, sizeof(cs4236b_eeprom));
|
||||
/* Copy default configuration data. */
|
||||
memcpy(&dev->eeprom_data[4], cs4236b_default, sizeof(cs4236b_default));
|
||||
|
||||
/* Load PnP resource data ROM. */
|
||||
FILE *fp = rom_fopen(PNP_ROM_CS4236B, "rb");
|
||||
if (fp) {
|
||||
(void) !fread(&(dev->eeprom_data[23]), 1, 8201, fp);
|
||||
uint16_t eeprom_pnp_offset = (dev->pnp_offset & 0x1ff) + 4;
|
||||
/* This is wrong. The header field only indicates PnP resource data length, and real chips use
|
||||
it to locate the firmware patch area, but we don't need any of that, so we can get away
|
||||
with pretending the whole ROM is PnP data, at least until we can get full EEPROM dumps. */
|
||||
dev->pnp_size = fread(&dev->eeprom_data[eeprom_pnp_offset], 1, sizeof(dev->eeprom_data) - eeprom_pnp_offset, fp);
|
||||
fclose(fp);
|
||||
}
|
||||
|
||||
/* Set content size. */
|
||||
dev->eeprom_data[2] = sizeof(cs4236b_eeprom) >> 8;
|
||||
dev->eeprom_data[3] = sizeof(cs4236b_eeprom) & 0xff;
|
||||
/* Populate EEPROM header if the PnP ROM was loaded. */
|
||||
if (dev->pnp_size) {
|
||||
dev->eeprom_data[0] = 0x55;
|
||||
dev->eeprom_data[1] = 0xbb;
|
||||
dev->eeprom_data[2] = dev->pnp_size >> 8;
|
||||
dev->eeprom_data[3] = dev->pnp_size;
|
||||
}
|
||||
|
||||
/* Set PnP card ID and EEPROM file name. */
|
||||
/* Patch PnP ROM and set EEPROM file name. */
|
||||
switch (dev->type) {
|
||||
case CRYSTAL_CS4235:
|
||||
dev->eeprom_data[8] = 0x05;
|
||||
dev->eeprom_data[16] = 0x08;
|
||||
dev->eeprom_data[26] = 0x25;
|
||||
dev->eeprom_data[44] = '5';
|
||||
if (dev->pnp_size) {
|
||||
dev->eeprom_data[8] = 0x05;
|
||||
dev->eeprom_data[16] = 0x08;
|
||||
dev->eeprom_data[26] = 0x25;
|
||||
dev->eeprom_data[44] = '5';
|
||||
}
|
||||
dev->nvr_path = "cs4235.nvr";
|
||||
break;
|
||||
|
||||
|
|
@ -775,14 +856,18 @@ cs423x_init(const device_t *info)
|
|||
break;
|
||||
|
||||
case CRYSTAL_CS4237B:
|
||||
dev->eeprom_data[26] = 0x37;
|
||||
dev->eeprom_data[44] = '7';
|
||||
if (dev->pnp_size) {
|
||||
dev->eeprom_data[26] = 0x37;
|
||||
dev->eeprom_data[44] = '7';
|
||||
}
|
||||
dev->nvr_path = "cs4237b.nvr";
|
||||
break;
|
||||
|
||||
case CRYSTAL_CS4238B:
|
||||
dev->eeprom_data[26] = 0x38;
|
||||
dev->eeprom_data[44] = '8';
|
||||
if (dev->pnp_size) {
|
||||
dev->eeprom_data[26] = 0x38;
|
||||
dev->eeprom_data[44] = '8';
|
||||
}
|
||||
dev->nvr_path = "cs4238b.nvr";
|
||||
break;
|
||||
|
||||
|
|
@ -807,8 +892,8 @@ cs423x_init(const device_t *info)
|
|||
/* Initialize I2C bus for the EEPROM. */
|
||||
dev->i2c = i2c_gpio_init("nvr_cs423x");
|
||||
|
||||
/* Initialize I2C EEPROM if the contents are valid. */
|
||||
if ((dev->eeprom_data[0] == 0x55) && (dev->eeprom_data[1] == 0xbb))
|
||||
/* Initialize I2C EEPROM if enabled. */
|
||||
if (!(info->local & CRYSTAL_NOEEPROM))
|
||||
dev->eeprom = i2c_eeprom_init(i2c_gpio_get_bus(dev->i2c), 0x50, dev->eeprom_data, sizeof(dev->eeprom_data), 1);
|
||||
|
||||
/* Initialize ISAPnP. */
|
||||
|
|
@ -836,6 +921,8 @@ cs423x_close(void *priv)
|
|||
{
|
||||
cs423x_t *dev = (cs423x_t *) priv;
|
||||
|
||||
cs423x_log("CS423x: close()\n");
|
||||
|
||||
/* Save EEPROM contents to file. */
|
||||
if (dev->eeprom) {
|
||||
cs423x_nvram(dev, 1);
|
||||
|
|
|
|||
Loading…
Reference in a new issue