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unittester: Add dummy main ports
Reads and writes mostly do nothing but log, although the status returns a dummy value of 0x04 (no command in flight, not waiting for anything, and no errors).
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parent
130d4094e1
commit
5279cd5d8d
1 changed files with 55 additions and 2 deletions
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@ -79,9 +79,46 @@ unittester_log(const char *fmt, ...)
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# define unittester_log(fmt, ...)
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#endif
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static void
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unittester_write(uint16_t port, uint8_t val, UNUSED(void *priv))
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{
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if (port == unittester.iobase_port+0x00) {
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/* Command port */
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/* TODO! --GM */
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unittester_log("[UT] W %02X Command\n", val);
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} else if (port == unittester.iobase_port+0x01) {
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/* Data port */
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/* TODO! --GM */
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unittester_log("[UT] W %02X Data\n", val);
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} else {
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/* Not handled here - possibly open bus! */
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}
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}
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static uint8_t
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unittester_read(uint16_t port, UNUSED(void *priv))
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{
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if (port == unittester.iobase_port+0x00) {
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/* Status port */
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/* TODO! --GM */
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unittester_log("[UT] R -- Status\n");
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return 0x04;
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} else if (port == unittester.iobase_port+0x01) {
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/* Data port */
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/* TODO! --GM */
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unittester_log("[UT] R -- Data\n");
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return 0xFE;
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} else {
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/* Not handled here - possibly open bus! */
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return 0xFF;
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}
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}
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static void
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unittester_trigger_write(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
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{
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unittester_log("[UT] Trigger value %02X -> FSM1 = %02X, FSM2 = %02X, IOBASE = %04X\n", val, unittester.fsm1, unittester.fsm2, unittester.iobase_port);
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/* Update FSM2 */
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switch (unittester.fsm2) {
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/* IDLE: Do nothing - FSM1 will put us in the right state. */
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@ -98,7 +135,20 @@ unittester_trigger_write(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
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/* WAIT IOBASE 0: Set high byte of temporary IOBASE and commit to the real IOBASE. */
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case UT_FSM2_WAIT_IOBASE_1:
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unittester.fsm2_new_iobase |= ((uint16_t)val)<<8;
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unittester_log("[UT] Remapping IOBASE: %04X -> %04X\n", val, unittester.iobase_port, unittester.fsm2_new_iobase);
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/* Unmap old IOBASE */
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if (unittester.iobase_port != 0xFFFF)
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io_removehandler(unittester.iobase_port, 2, unittester_read, NULL, NULL, unittester_write, NULL, NULL, NULL);
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unittester.iobase_port = 0xFFFF;
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/* Map new IOBASE */
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unittester.iobase_port = unittester.fsm2_new_iobase;
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if (unittester.iobase_port != 0xFFFF)
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io_sethandler(unittester.iobase_port, 2, unittester_read, NULL, NULL, unittester_write, NULL, NULL, NULL);
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/* Reset FSM2 to IDLE */
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unittester.fsm2 = UT_FSM2_IDLE;
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break;
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}
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@ -128,6 +178,7 @@ unittester_trigger_write(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
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break;
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case 'x':
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if (unittester.fsm1 == UT_FSM1_WAIT_x) {
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unittester_log("[UT] Config activated, awaiting new IOBASE\n");
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unittester.fsm2 = UT_FSM2_WAIT_IOBASE_0;
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}
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unittester.fsm1 = UT_FSM1_WAIT_8;
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@ -137,8 +188,6 @@ unittester_trigger_write(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
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unittester.fsm1 = UT_FSM1_WAIT_8;
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break;
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}
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unittester_log("[UT] Trigger value %02X -> FSM1 = %02X, FSM2 = %02X, IOBASE = %04X\n", val, unittester.fsm1, unittester.fsm2, unittester.iobase_port);
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}
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static void *
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@ -157,6 +206,10 @@ unittester_close(UNUSED(void *priv))
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{
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io_removehandler(unittester.trigger_port, 1, NULL, NULL, NULL, unittester_trigger_write, NULL, NULL, NULL);
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if (unittester.iobase_port != 0xFFFF)
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io_removehandler(unittester.iobase_port, 2, unittester_read, NULL, NULL, unittester_write, NULL, NULL, NULL);
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unittester.iobase_port = 0xFFFF;
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unittester_log("[UT] 86Box Unit Tester closed\n");
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}
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