From 3a22930c07f6f012381f41ede9021473b17a3f63 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Thu, 9 Jan 2025 23:24:58 +0100 Subject: [PATCH] And Cirrus per the previous commit. Improved the byte swap fix introduced time ago, this time by making it trigger on banked writes when needed. --- src/video/vid_cl54xx.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c index 4e7d1ac09..bc54d0d7c 100644 --- a/src/video/vid_cl54xx.c +++ b/src/video/vid_cl54xx.c @@ -1361,7 +1361,7 @@ gd54xx_in(uint16_t addr, void *priv) 32-bit (Pre-5434)/64-bit (5434 and up) DRAM data bus width for 2M of memory */ - ret |= (gd54xx_is_5434(svga)) ? 0x98 : 0x18; + ret |= 0x18; break; case 4096: ret |= 0x98; /*64-bit (5434 and up) DRAM data bus width for 4M of memory*/ @@ -2281,6 +2281,9 @@ gd54xx_writew(uint32_t addr, uint16_t val, void *priv) if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) { + if ((gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) && (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)) + val = (val >> 8) | (val << 8); + gd54xx_write(addr, val, gd54xx); gd54xx_write(addr + 1, val >> 8, gd54xx); return; @@ -2308,6 +2311,9 @@ gd54xx_writel(uint32_t addr, uint32_t val, void *priv) if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) { + if ((gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) && (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)) + val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24); + gd54xx_write(addr, val, gd54xx); gd54xx_write(addr + 1, val >> 8, gd54xx); gd54xx_write(addr + 2, val >> 16, gd54xx); @@ -3661,9 +3667,6 @@ gd54xx_mem_sys_src(gd54xx_t *gd54xx, uint32_t cpu_dat, uint32_t count) mask_shift = 31 - byte_pos; if (!(gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)) cpu_dat >>= byte_pos; - else if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY) - cpu_dat = ((cpu_dat & 0xff000000) >> 24) | ((cpu_dat & 0x00ff0000) >> 8) | - ((cpu_dat & 0x0000ff00) << 8) | ((cpu_dat & 0x000000ff) << 24); } else mask_shift = 7;