mirror of
https://github.com/86Box/86Box.git
synced 2025-01-22 09:11:50 -05:00
SCAMP: Reworked a lot of stuff, backfill EMS should now also work.
This commit is contained in:
OBattler
parent
bf0e243c92
commit
ef8a3d8d42
1 changed files with 520 additions and 328 deletions
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@ -47,13 +47,35 @@
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#define ID_VL82C311 0xd6
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#define RAMMAP_REMP386 (1 << 4)
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#define RAMMAP_ROMMOV 0x60
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#define RAMMAP_ROMMOV1 (1 << 6)
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#define RAMMAP_ROMMOV0 (1 << 5)
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#define RAMMAP_REMP384 (1 << 4)
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#define EMSEN1_EMSMAP (1 << 4)
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#define EMSEN1_BFENAB (1 << 6)
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#define EMSEN1_EMSENAB (1 << 7)
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#define NR_ELEMS(x) (sizeof(x) / sizeof(x[0]))
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#define EMS_MAXPAGE 4
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#define EMS_PGSIZE 16384
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#define EMS_PGMASK 16383
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#define MEM_FLAG_SLOTBUS 0x40
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#define MEM_FLAG_REMAP 0x20
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#define MEM_FLAG_MEMCARD 0x10
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#define MEM_FLAG_EMS 0x08
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#define MEM_FLAG_ROMCS 0x04
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#define MEM_FLAG_READ 0x02
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#define MEM_FLAG_WRITE 0x01
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#define MEM_FMASK_SLOTBUS 0x40
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#define MEM_FMASK_REMAP 0x20
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#define MEM_FMASK_MEMCARD 0x10
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#define MEM_FMASK_EMS 0x08
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#define MEM_FMASK_ROMCS 0x04
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#define MEM_FMASK_RW 0x03
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/*Commodore SL386SX requires proper memory slot decoding to detect memory size.
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Therefore we emulate the SCAMP memory address decoding, and therefore are
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limited to the DRAM combinations supported by the actual chip*/
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@ -72,10 +94,12 @@ typedef struct ram_struct_t {
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int bank;
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} ram_struct_t;
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typedef struct ems_struct_t {
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void *parent;
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int segment;
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} ems_struct_t;
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typedef struct card_mem_t {
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int in_ram;
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uint32_t virt_addr;
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uint32_t phys_addr;
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uint8_t *mem;
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} mem_page_t;
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typedef struct scamp_t {
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int cfg_index;
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@ -85,13 +109,10 @@ typedef struct scamp_t {
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int ems_index;
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int ems_autoinc;
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uint16_t ems[0x24];
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mem_mapping_t ems_mappings[20]; /*a0000-effff*/
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uint32_t mappings[20];
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uint16_t ems[64];
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mem_mapping_t ram_mapping[2];
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ram_struct_t ram_struct[2];
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ems_struct_t ems_struct[20];
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uint32_t ram_virt_base[2];
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uint32_t ram_phys_base[2];
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@ -101,7 +122,13 @@ typedef struct scamp_t {
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int ram_interleaved[2];
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int ibank_shift[2];
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int ram_flags[24];
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int mem_flags[64];
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mem_mapping_t mem_mappings[64]; /* The entire first 1 MB of memory space. */
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mem_page_t mem_pages[64];
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uint32_t card_mem_size;
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uint8_t *card_mem;
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mem_page_t card_pages[4];
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port_92_t *port_92;
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} scamp_t;
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@ -149,6 +176,70 @@ static const struct {
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{ { BANK_1M_INTERLEAVED, BANK_4M_INTERLEAVED }, 0}, /*Undocumented - probably wrong!*/
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};
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#ifdef ENABLE_SCAMP_LOG
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int scamp_do_log = ENABLE_SCAMP_LOG;
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static void
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scamp_log(const char *fmt, ...)
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{
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va_list ap;
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if (scamp_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define scamp_log(fmt, ...)
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#endif
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/* Read one byte from paged RAM. */
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static uint8_t
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scamp_mem_readb(uint32_t addr, void *priv)
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{
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mem_page_t *dev = (mem_page_t *) priv;
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uint8_t ret = 0xff;
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if (dev->mem != NULL)
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ret = *(uint8_t *) &(dev->mem[addr & EMS_PGMASK]);
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return ret;
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}
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/* Read one word from paged RAM. */
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static uint16_t
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scamp_mem_readw(uint32_t addr, void *priv)
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{
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mem_page_t *dev = (mem_page_t *) priv;
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uint16_t ret = 0xffff;
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if (dev->mem != NULL)
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ret = *(uint16_t *) &(dev->mem[addr & EMS_PGMASK]);
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return ret;
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}
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/* Write one byte to paged RAM. */
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static void
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scamp_mem_writeb(uint32_t addr, uint8_t val, void *priv)
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{
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mem_page_t *dev = (mem_page_t *) priv;
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if (dev->mem != NULL)
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*(uint8_t *) &(dev->mem[addr & EMS_PGMASK]) = val;
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}
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/* Write one word to paged RAM. */
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static void
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scamp_mem_writew(uint32_t addr, uint16_t val, void *priv)
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{
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mem_page_t *dev = (mem_page_t *) priv;
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if (dev->mem != NULL)
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*(uint16_t *) &(dev->mem[addr & EMS_PGMASK]) = val;
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}
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/* The column bits masked when using 256kbit DRAMs in 4Mbit mode aren't contiguous,
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so we use separate routines for that special case */
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static uint8_t
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@ -334,20 +425,23 @@ recalc_mappings(void *priv)
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/* Once the BIOS programs the correct DRAM configuration, switch to regular
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linear memory mapping */
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if (cur_rammap == ram_configs[dev->ram_config].rammap) {
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mem_mapping_set_handler(&ram_low_mapping,
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mem_read_ram, mem_read_ramw, mem_read_raml,
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mem_write_ram, mem_write_ramw, mem_write_raml);
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mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000);
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mem_mapping_disable(&ram_low_mapping);
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for (uint8_t i = 0; i < 40; i++)
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mem_mapping_enable(&(dev->mem_mappings[i]));
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if (mem_size > 1024)
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mem_set_mem_state_both((1 << 20), (mem_size - 1024) << 10, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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mem_mapping_enable(&ram_high_mapping);
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return;
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} else {
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mem_mapping_set_handler(&ram_low_mapping,
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ram_mirrored_read, NULL, NULL,
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ram_mirrored_write, NULL, NULL);
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mem_mapping_disable(&ram_low_mapping);
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}
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for (uint8_t i = 0; i < 40; i++)
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mem_mapping_disable(&(dev->mem_mappings[i]));
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if (rammap[cur_rammap].bank[0] == BANK_NONE)
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bank_nr = 1;
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@ -502,6 +596,7 @@ recalc_mappings(void *priv)
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break;
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}
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}
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switch (rammap[cur_rammap].bank[bank_nr]) {
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case BANK_256K:
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case BANK_1M:
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@ -550,124 +645,111 @@ recalc_mappings(void *priv)
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break;
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}
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}
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}
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static void
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recalc_sltptr(scamp_t *dev)
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{
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uint32_t sltptr = dev->cfg_regs[CFG_SLTPTR] << 16;
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if (sltptr >= 0xa0000 && sltptr < 0x100000)
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sltptr = 0x100000;
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if (sltptr > 0xfe0000)
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sltptr = 0xfe0000;
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if (sltptr >= 0xa0000) {
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mem_set_mem_state(0, 0xa0000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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mem_set_mem_state(0x100000, sltptr - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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mem_set_mem_state(sltptr, 0x1000000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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} else {
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mem_set_mem_state(0, sltptr, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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mem_set_mem_state(sltptr, 0xa0000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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mem_set_mem_state(0x100000, 0xf00000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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}
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static uint8_t
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scamp_ems_read(uint32_t addr, void *priv)
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{
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const ems_struct_t *ems = (ems_struct_t *) priv;
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const scamp_t *dev = ems->parent;
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int segment = ems->segment;
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addr = (addr & 0x3fff) | dev->mappings[segment];
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return ram[addr];
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}
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static void
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scamp_ems_write(uint32_t addr, uint8_t val, void *priv)
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scamp_mem_update_state(scamp_t *dev, uint32_t addr, uint32_t size, uint8_t new_flags, uint8_t mask)
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{
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const ems_struct_t *ems = (ems_struct_t *) priv;
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const scamp_t *dev = ems->parent;
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int segment = ems->segment;
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int read_ext = MEM_READ_EXTERNAL;
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int write_ext = MEM_WRITE_EXTERNAL;
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addr = (addr & 0x3fff) | dev->mappings[segment];
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ram[addr] = val;
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}
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if ((addr < 0x00100000) && ((new_flags ^ dev->mem_flags[addr / EMS_PGSIZE]) & mask)) {
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dev->mem_flags[addr / EMS_PGSIZE] &= ~mask;
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dev->mem_flags[addr / EMS_PGSIZE] |= new_flags;
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static void
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scamp_mem_update_state(scamp_t *dev, uint32_t addr, uint32_t size)
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{
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uint8_t flags;
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new_flags = dev->mem_flags[addr / EMS_PGSIZE];
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if ((addr >= 0x000a0000) && (addr < 0x00100000)) {
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flags = dev->ram_flags[(addr - 0x000a0000) >> 14];
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if (new_flags & MEM_FLAG_ROMCS) {
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read_ext = MEM_READ_ROMCS;
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write_ext = MEM_WRITE_ROMCS;
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}
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if (flags & 4)
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if (new_flags & (MEM_FLAG_REMAP | MEM_FLAG_SLOTBUS)) {
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scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (REMAP)\n", addr, addr + size - 1, new_flags);
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mem_set_mem_state(addr, size, read_ext | write_ext);
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} else if (new_flags & (MEM_FLAG_EMS | MEM_FLAG_MEMCARD)) {
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scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (EMS)\n", addr, addr + size - 1, new_flags);
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else switch (flags & 3) {
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} else switch (new_flags & (MEM_FLAG_READ | MEM_FLAG_WRITE)) {
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (RE | WE)\n", addr, addr + size - 1, new_flags);
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mem_set_mem_state(addr, size, read_ext | write_ext);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (RE | WI)\n", addr, addr + size - 1, new_flags);
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mem_set_mem_state(addr, size, read_ext | MEM_WRITE_INTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
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scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (RI | WE)\n", addr, addr + size - 1, new_flags);
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | write_ext);
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break;
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case 3:
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scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (RI | WI)\n", addr, addr + size - 1, new_flags);
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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default:
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break;
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}
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}
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flushmmucache_nopc();
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}
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static int
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is_seg_in_ram(scamp_t *dev, uint8_t s)
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{
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mem_page_t *mp = (mem_page_t *) dev->mem_mappings[s].priv;
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const int ret = mp->in_ram;
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return ret;
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}
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static void
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recalc_ems(scamp_t *dev)
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{
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const uint32_t ems_base[12] = {
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0xc0000, 0xc4000, 0xc8000, 0xcc000,
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0xd0000, 0xd4000, 0xd8000, 0xdc000,
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0xe0000, 0xe4000, 0xe8000, 0xec000
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};
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uint32_t new_mappings[20];
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uint16_t ems_enable;
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const uint8_t seg_xlat[12] = { 40, 41, 42, 43, 52, 53, 54, 55, 44, 45, 46, 47 };
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const uint16_t seg_enable = dev->cfg_regs[CFG_EMSEN2] | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 8);
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for (int segment = 0; segment < 20; segment++)
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new_mappings[segment] = 0xa0000 + segment * 0x4000;
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for (uint8_t s = 40; s < 60; s++) {
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dev->mem_pages[s].phys_addr = dev->mem_pages[s].virt_addr;
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dev->mem_pages[s].mem = ram + dev->mem_pages[s].phys_addr;
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if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB)
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ems_enable = dev->cfg_regs[CFG_EMSEN2] | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 8);
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else
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ems_enable = 0;
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if (is_seg_in_ram(dev, s))
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mem_mapping_set_exec(&(dev->mem_mappings[s]), dev->mem_pages[s].mem);
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for (int segment = 0; segment < 12; segment++) {
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if (ems_enable & (1 << segment)) {
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uint32_t phys_addr = dev->ems[segment] << 14;
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/*If physical address is in remapped memory then adjust down to a0000-fffff range*/
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if ((dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) && phys_addr >= (mem_size * 1024)
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&& phys_addr < ((mem_size + 384) * 1024))
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phys_addr = (phys_addr - mem_size * 1024) + 0xa0000;
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new_mappings[(ems_base[segment] - 0xa0000) >> 14] = phys_addr;
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}
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scamp_mem_update_state(dev, s * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_EMS);
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}
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for (int segment = 0; segment < 20; segment++) {
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if (new_mappings[segment] != dev->mappings[segment]) {
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dev->mappings[segment] = new_mappings[segment];
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if (new_mappings[segment] < (mem_size * 1024)) {
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mem_mapping_set_exec(&dev->ems_mappings[segment], ram + dev->mappings[segment]);
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mem_mapping_enable(&dev->ems_mappings[segment]);
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dev->ram_flags[segment] |= 0x04;
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} else {
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mem_mapping_disable(&dev->ems_mappings[segment]);
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dev->ram_flags[segment] &= 0xfb;
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}
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for (uint8_t i = 0; i < 36; i++) {
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uint8_t s = (i < 12) ? (i + 48) : (i + 4);
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uint8_t on = (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB);
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uint32_t phys_addr = dev->ems[i] << 14;
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scamp_mem_update_state(dev, 0xa0000 + segment * 0x4000, 0x4000);
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if (i < 12) {
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if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSMAP)
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s = seg_xlat[i];
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on = on && (seg_enable & (1 << i));
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} else
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on = on && (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_BFENAB);
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if (on) {
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dev->mem_pages[s].phys_addr = phys_addr;
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dev->mem_pages[s].mem = ram + dev->mem_pages[s].phys_addr;
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if (is_seg_in_ram(dev, s))
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mem_mapping_set_exec(&(dev->mem_mappings[s]), dev->mem_pages[s].mem);
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scamp_mem_update_state(dev, s * EMS_PGSIZE, EMS_PGSIZE, MEM_FLAG_EMS, MEM_FMASK_EMS);
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} else if (i >= 12) {
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dev->mem_pages[s].phys_addr = dev->mem_pages[s].virt_addr;
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dev->mem_pages[s].mem = ram + dev->mem_pages[s].phys_addr;
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if (is_seg_in_ram(dev, s))
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mem_mapping_set_exec(&(dev->mem_mappings[s]), dev->mem_pages[s].mem);
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scamp_mem_update_state(dev, s * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_EMS);
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}
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}
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@ -677,32 +759,11 @@ recalc_ems(scamp_t *dev)
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static void
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shadow_control(scamp_t *dev, uint32_t addr, uint32_t size, int state)
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{
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dev->ram_flags[(addr - 0x000a0000) >> 14] &= 0xfc;
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dev->ram_flags[(addr - 0x000a0000) >> 14] |= state;
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if (size == 0x8000) {
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dev->ram_flags[((addr - 0x000a0000) >> 14) + 1] &= 0xfc;
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dev->ram_flags[((addr - 0x000a0000) >> 14) + 1] |= state;
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}
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switch (state) {
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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break;
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case 1:
|
||||
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
|
||||
break;
|
||||
case 2:
|
||||
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
|
||||
break;
|
||||
case 3:
|
||||
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
scamp_mem_update_state(dev, addr, size);
|
||||
scamp_mem_update_state(dev, addr, EMS_PGSIZE, state, MEM_FMASK_RW);
|
||||
scamp_mem_update_state(dev, addr + EMS_PGSIZE, EMS_PGSIZE, state, MEM_FMASK_RW);
|
||||
} else
|
||||
scamp_mem_update_state(dev, addr, size, state, MEM_FMASK_RW);
|
||||
|
||||
flushmmucache_nopc();
|
||||
}
|
||||
|
|
@ -710,14 +771,23 @@ shadow_control(scamp_t *dev, uint32_t addr, uint32_t size, int state)
|
|||
static void
|
||||
shadow_recalc(scamp_t *dev)
|
||||
{
|
||||
uint8_t abaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_ABAXS];
|
||||
uint8_t caxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_CAXS];
|
||||
uint8_t daxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_DAXS];
|
||||
uint8_t feaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_FEAXS];
|
||||
uint8_t abaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) ? 0 : dev->cfg_regs[CFG_ABAXS];
|
||||
uint8_t caxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) ? 0 : dev->cfg_regs[CFG_CAXS];
|
||||
uint8_t daxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) ? 0 : dev->cfg_regs[CFG_DAXS];
|
||||
uint8_t feaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) ? 0 : dev->cfg_regs[CFG_FEAXS];
|
||||
|
||||
/*Enabling remapping will disable all shadowing*/
|
||||
if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386)
|
||||
mem_remap_top(384);
|
||||
if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384)
|
||||
mem_remap_top_nomid(384);
|
||||
else
|
||||
mem_remap_top_nomid(0);
|
||||
|
||||
for (uint8_t i = 40; i < 64; i++) {
|
||||
if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384)
|
||||
scamp_mem_update_state(dev, (i * EMS_PGSIZE), EMS_PGSIZE, MEM_FLAG_REMAP, MEM_FMASK_REMAP);
|
||||
else
|
||||
scamp_mem_update_state(dev, (i * EMS_PGSIZE), EMS_PGSIZE, 0x00, MEM_FMASK_REMAP);
|
||||
}
|
||||
|
||||
shadow_control(dev, 0xa0000, 0x4000, abaxs & 3);
|
||||
shadow_control(dev, 0xa0000, 0x4000, abaxs & 3);
|
||||
|
|
@ -748,6 +818,97 @@ shadow_recalc(scamp_t *dev)
|
|||
shadow_control(dev, 0xf8000, 0x8000, (feaxs >> 6) & 3);
|
||||
}
|
||||
|
||||
static void
|
||||
recalc_sltptr(scamp_t *dev)
|
||||
{
|
||||
uint32_t sltptr = dev->cfg_regs[CFG_SLTPTR] << 16;
|
||||
|
||||
if (sltptr >= 0xa0000 && sltptr < 0x100000)
|
||||
sltptr = 0x100000;
|
||||
if (sltptr > 0xfe0000)
|
||||
sltptr = 0xfe0000;
|
||||
|
||||
if (sltptr >= 0xa0000) {
|
||||
for (uint8_t i = 0; i < 40; i++)
|
||||
scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_SLOTBUS);
|
||||
|
||||
mem_set_mem_state(0x100000, sltptr - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
|
||||
mem_set_mem_state(sltptr, 0x1000000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
|
||||
|
||||
if ((sltptr >= 0x40000) && (sltptr <= 0x90000)) {
|
||||
dev->cfg_regs[CFG_EMSEN1] &= ~EMSEN1_BFENAB;
|
||||
recalc_ems(dev);
|
||||
}
|
||||
} else {
|
||||
for (uint8_t i = 0; i < (sltptr / EMS_PGSIZE); i++)
|
||||
scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_SLOTBUS);
|
||||
|
||||
for (uint8_t i = (sltptr / EMS_PGSIZE); i < 40; i++)
|
||||
scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, MEM_FLAG_SLOTBUS, MEM_FMASK_SLOTBUS);
|
||||
|
||||
mem_set_mem_state(sltptr, 0xa0000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
|
||||
mem_set_mem_state(0x100000, 0xf00000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
|
||||
}
|
||||
|
||||
flushmmucache_nopc();
|
||||
}
|
||||
|
||||
static void
|
||||
recalc_rommov(scamp_t *dev)
|
||||
{
|
||||
switch ((dev->cfg_regs[CFG_RAMMAP] & RAMMAP_ROMMOV) >> 5) {
|
||||
case 0x00:
|
||||
scamp_mem_update_state(dev, 0x000c0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000c4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000c8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000cc000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
|
||||
scamp_mem_update_state(dev, 0x000e0000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000e4000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000e8000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000ec000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
scamp_mem_update_state(dev, 0x000c0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000c4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000c8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000cc000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
|
||||
scamp_mem_update_state(dev, 0x000e0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000e4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000e8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000ec000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
scamp_mem_update_state(dev, 0x000c0000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000c4000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000c8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000cc000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
|
||||
scamp_mem_update_state(dev, 0x000e0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000e4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000e8000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000ec000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
break;
|
||||
|
||||
case 0x03:
|
||||
scamp_mem_update_state(dev, 0x000c0000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000c4000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000c8000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000cc000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
|
||||
scamp_mem_update_state(dev, 0x000e0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000e4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000e8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
scamp_mem_update_state(dev, 0x000ec000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS);
|
||||
break;
|
||||
}
|
||||
|
||||
flushmmucache_nopc();
|
||||
}
|
||||
|
||||
static void
|
||||
scamp_write(uint16_t addr, uint8_t val, void *priv)
|
||||
{
|
||||
|
|
@ -755,7 +916,7 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
|
|||
|
||||
switch (addr) {
|
||||
case 0xe8:
|
||||
dev->ems_index = val & 0x1f;
|
||||
dev->ems_index = val & 0x3f;
|
||||
dev->ems_autoinc = val & 0x40;
|
||||
break;
|
||||
|
||||
|
|
@ -785,12 +946,14 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
|
|||
switch (dev->cfg_index) {
|
||||
case CFG_SLTPTR:
|
||||
recalc_sltptr(dev);
|
||||
recalc_ems(dev);
|
||||
break;
|
||||
|
||||
case CFG_RAMMAP:
|
||||
recalc_mappings(dev);
|
||||
mem_mapping_disable(&ram_remapped_mapping);
|
||||
shadow_recalc(dev);
|
||||
recalc_rommov(dev);
|
||||
break;
|
||||
|
||||
case CFG_EMSEN1:
|
||||
|
|
@ -914,9 +1077,8 @@ scamp_init(UNUSED(const device_t *info))
|
|||
mem_mapping_set_handler(&ram_low_mapping,
|
||||
ram_mirrored_read, NULL, NULL,
|
||||
ram_mirrored_write, NULL, NULL);
|
||||
mem_mapping_disable(&ram_mid_mapping);
|
||||
mem_mapping_disable(&ram_high_mapping);
|
||||
mem_mapping_set_addr(&ram_mid_mapping, 0xf0000, 0x10000);
|
||||
mem_mapping_set_exec(&ram_mid_mapping, ram + 0xf0000);
|
||||
|
||||
addr = 0;
|
||||
for (uint8_t c = 0; c < 2; c++) {
|
||||
|
|
@ -988,15 +1150,45 @@ scamp_init(UNUSED(const device_t *info))
|
|||
|
||||
mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
|
||||
|
||||
for (uint8_t c = 0; c < 20; c++) {
|
||||
dev->ems_struct[c].parent = dev;
|
||||
dev->ems_struct[c].segment = c;
|
||||
mem_mapping_add(&dev->ems_mappings[c],
|
||||
0xa0000 + c * 0x4000, 0x4000,
|
||||
scamp_ems_read, NULL, NULL,
|
||||
scamp_ems_write, NULL, NULL,
|
||||
ram + 0xa0000 + c * 0x4000, MEM_MAPPING_INTERNAL, (void *) &dev->ems_struct[c]);
|
||||
dev->mappings[c] = 0xa0000 + c * 0x4000;
|
||||
for (uint8_t i = 0; i < 12; i++)
|
||||
dev->ems[i] = (0x000c0000 + (i * EMS_PGSIZE)) >> 14;
|
||||
|
||||
for (uint8_t i = 0; i < 24; i++)
|
||||
dev->ems[i + 12] = (0x00040000 + (i * EMS_PGSIZE)) >> 14;
|
||||
|
||||
for (uint8_t i = 0; i < 64; i++) {
|
||||
dev->mem_pages[i].in_ram = 1;
|
||||
dev->mem_pages[i].virt_addr = i * EMS_PGSIZE;
|
||||
dev->mem_pages[i].phys_addr = dev->mem_pages[i].virt_addr;
|
||||
dev->mem_pages[i].mem = ram + dev->mem_pages[i].phys_addr;
|
||||
|
||||
mem_mapping_add(&(dev->mem_mappings[i]),
|
||||
i * EMS_PGSIZE, EMS_PGSIZE,
|
||||
scamp_mem_readb, scamp_mem_readw, NULL,
|
||||
scamp_mem_writeb, scamp_mem_writew, NULL,
|
||||
dev->mem_pages[i].mem, MEM_MAPPING_INTERNAL,
|
||||
&(dev->mem_pages[i]));
|
||||
|
||||
if (i < 40) {
|
||||
mem_mapping_disable(&(dev->mem_mappings[i]));
|
||||
|
||||
scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, MEM_FLAG_READ | MEM_FLAG_WRITE, MEM_FMASK_RW);
|
||||
} else {
|
||||
/* This is needed to the state update actually occurs. */
|
||||
dev->mem_flags[i] = MEM_FLAG_READ | MEM_FLAG_WRITE;
|
||||
scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_RW);
|
||||
|
||||
if (i >= 60)
|
||||
scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS);
|
||||
}
|
||||
}
|
||||
|
||||
dev->card_mem = NULL;
|
||||
|
||||
for (uint8_t i = 0; i < 4; i++) {
|
||||
dev->card_pages[i].virt_addr = i * EMS_PGSIZE;
|
||||
dev->card_pages[i].phys_addr = dev->card_pages[i].virt_addr;
|
||||
dev->card_pages[i].mem = dev->card_mem + dev->card_pages[i].phys_addr;
|
||||
}
|
||||
|
||||
dev->port_92 = device_add(&port_92_device);
|
||||
|
|
|
|||
Loading…
Reference in a new issue