Commit graph

4 commits

Author SHA1 Message Date
Liav A
0b7fc525e1 Interrupts: Simplify IRQ disabling & enabling in IRQController(s)
Instead of blindly setting masks, if we want to disable an IRQ and it's
already masked, we just return. The same happens if we want to enable an
IRQ and it's unmasked.
2020-03-24 16:15:33 +01:00
Liav A
f86be46c98 Kernel: Abstract IRQ controller handling from Interrupt handlers
Now we don't send raw numbers, but we let the IRQController object to
figure out the correct IRQ number.
This helps in a situation when we have 2 or more IOAPICs, so if IOAPIC
1 is assigned for IRQs 0-23 and IOAPIC 2 is assigned for IRQs 24-47,
if an IRQHandler of IRQ 25 invokes disable() for example, it will call
his responsible IRQController (IOAPIC 2), and the IRQController will
subtract the IRQ number with his assigned offset, and the result is that
the second redirection entry in IOAPIC 2 will be masked.
2020-03-24 16:15:33 +01:00
Liav A
30fc78bfaf Kernel: Acquire ISA interrupt overrides from Interrupt Management
Also, InterruptDisabler were added to prevent critical function from
being interrupted. In addition, the interrupt numbers are abstracted
from IDT offsets, thus, allowing to create a better routing scheme
when using IOAPICs for interrupt redirection.
2020-03-06 10:32:32 +01:00
Liav A
e760ebcacb Kernel: Add the IOAPIC class
This class inherits from IRQController class, and represents
the 82093AA IOAPIC chip.
2020-02-24 11:27:03 +01:00