Timon Kruiper 6a8581855d Kernel/aarch64: Flush entire TLB cache when changing TTBR0_EL1 ... Setting the page table base register (ttbr0_el1) is not enough, and will not flush the TLB caches, in contrary with x86_64 where setting the CR3 register will actually flush the caches. This commit adds the necessary code to properly flush the TLB caches when context switching. This commit also changes Processor::flush_tlb_local to use the vmalle1 variant, as previously we would be flushing the tlb's of all the cores in the inner-shareable domain.		2023-04-06 21:19:58 +03:00
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aarch64	Kernel/aarch64: Flush entire TLB cache when changing TTBR0_EL1	2023-04-06 21:19:58 +03:00
x86_64	Kernel: Store a pointer to the owner process in PageDirectory	2023-04-06 20:30:03 +03:00
CPU.h
CurrentTime.h
DebugOutput.h
DeferredCallEntry.h
DeferredCallPool.cpp	Kernel: Move deferred call code into separate DeferredCallPool class	2023-04-03 20:01:28 -06:00
DeferredCallPool.h	Kernel: Move deferred call code into separate DeferredCallPool class	2023-04-03 20:01:28 -06:00
Delay.h
init.cpp	Kernel: Simplify Process factory functions	2023-04-04 10:33:42 +02:00
InterruptManagement.h
Interrupts.h
IRQController.h
mcontext.h
PageDirectory.h
PageFault.cpp	Kernel: Remove heuristics for detecting malformed malloc memory access	2023-03-01 19:36:53 -07:00
PageFault.h	Kernel/aarch64: Handle instruction aborts	2023-02-08 18:19:48 +00:00
Processor.cpp
Processor.h
ProcessorSpecificDataID.h
RegisterState.h
SafeMem.h
SmapDisabler.h
ThreadRegisters.h
TrapFrame.h