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The hierarchy is AHCIController, AHCIPortHandler, AHCIPort and SATADiskDevice. Each AHCIController has at least one AHCIPortHandler. An AHCIPortHandler is an interrupt handler that takes care of enumeration of handled AHCI ports when an interrupt occurs. Each AHCIPort takes care of one SATADiskDevice, and later on we can add support for Port multiplier. When we implement support of Message signalled interrupts, we can spawn many AHCIPortHandlers, and allow each one of them to be responsible for a set of AHCIPorts.
103 lines
4.1 KiB
C++
103 lines
4.1 KiB
C++
/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <Kernel/Storage/AHCIPortHandler.h>
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namespace Kernel {
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NonnullRefPtr<AHCIPortHandler> AHCIPortHandler::create(AHCIController& controller, u8 irq, AHCI::MaskedBitField taken_ports)
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{
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return adopt(*new AHCIPortHandler(controller, irq, taken_ports));
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}
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AHCIPortHandler::AHCIPortHandler(AHCIController& controller, u8 irq, AHCI::MaskedBitField taken_ports)
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: IRQHandler(irq)
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, m_parent_controller(controller)
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, m_taken_ports(taken_ports)
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, m_pending_ports_interrupts(create_pending_ports_interrupts_bitfield())
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{
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// FIXME: Use the number of taken ports to determine how many pages we should allocate.
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for (size_t index = 0; index < (((size_t)AHCI::Limits::MaxPorts * 512) / PAGE_SIZE); index++) {
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m_identify_metadata_pages.append(MM.allocate_supervisor_physical_page().release_nonnull());
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}
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// Clear pending interrupts, if there are any!
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m_pending_ports_interrupts.set_all();
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enable_irq();
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for (auto index : taken_ports.to_vector()) {
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auto port = AHCIPort::create(*this, static_cast<volatile AHCI::PortRegisters&>(controller.hba().port_regs[index]), index);
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m_handled_ports.set(index, port);
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port->reset();
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}
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}
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void AHCIPortHandler::enumerate_ports(Function<void(const AHCIPort&)> callback) const
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{
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for (auto& port : m_handled_ports) {
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callback(*port.value);
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}
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}
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RefPtr<AHCIPort> AHCIPortHandler::port_at_index(u32 port_index) const
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{
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VERIFY(m_taken_ports.is_set_at(port_index));
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auto it = m_handled_ports.find(port_index);
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if (it == m_handled_ports.end())
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return nullptr;
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return (*it).value;
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}
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PhysicalAddress AHCIPortHandler::get_identify_metadata_physical_region(u32 port_index) const
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{
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dbgln_if(AHCI_DEBUG, "AHCI Port Handler: Get identify metadata physical address of port {} - {}", port_index, (port_index * 512) / PAGE_SIZE);
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return m_identify_metadata_pages[(port_index * 512) / PAGE_SIZE].paddr().offset((port_index * 512) % PAGE_SIZE);
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}
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AHCI::MaskedBitField AHCIPortHandler::create_pending_ports_interrupts_bitfield() const
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{
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return AHCI::MaskedBitField((volatile u32&)m_parent_controller->hba().control_regs.is, m_taken_ports.bit_mask());
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}
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AHCI::HBADefinedCapabilities AHCIPortHandler::hba_capabilities() const
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{
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return m_parent_controller->hba_capabilities();
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}
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AHCIPortHandler::~AHCIPortHandler()
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{
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}
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void AHCIPortHandler::handle_irq(const RegisterState&)
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{
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for (auto port_index : m_pending_ports_interrupts.to_vector()) {
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auto port = m_handled_ports.get(port_index);
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VERIFY(port.has_value());
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port.value()->handle_interrupt();
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// We do this to clear the pending interrupt after we handled it.
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m_pending_ports_interrupts.set_at(port_index);
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}
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}
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}
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