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spi: s3c64xx: add spi port configuration for Exynos Auto v9 SoC
Add exynosautov9 spi port configuration. It supports up to 12 spis so MAX_SPI_PORTS should be increased from 6 to 12. It has DIV_4 as the default internal clock divider and an internal loopback mode to run a loopback test. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Andi Shyti <andi@etezian.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20220629102304.65712-5-chanho61.park@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
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1 changed files with 17 additions and 1 deletions
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@ -18,7 +18,7 @@
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#include <linux/platform_data/spi-s3c64xx.h>
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#define MAX_SPI_PORTS 6
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#define MAX_SPI_PORTS 12
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#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
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#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
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#define AUTOSUSPEND_TIMEOUT 2000
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@ -1451,6 +1451,19 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
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.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
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};
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static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
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.fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
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0x7f, 0x7f, 0x7f, 0x7f},
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.rx_lvl_offset = 15,
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.tx_st_done = 25,
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.clk_div = 4,
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.high_speed = true,
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.clk_from_cmu = true,
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.clk_ioclk = true,
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.has_loopback = true,
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.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
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};
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static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
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.fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
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.rx_lvl_offset = 15,
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@ -1492,6 +1505,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
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{ .compatible = "samsung,exynos5433-spi",
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.data = (void *)&exynos5433_spi_port_config,
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},
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{ .compatible = "samsung,exynosautov9-spi",
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.data = (void *)&exynosautov9_spi_port_config,
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},
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{ .compatible = "tesla,fsd-spi",
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.data = (void *)&fsd_spi_port_config,
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},
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