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drivers/perf: riscv: Do not allow invalid raw event config

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The SBI specification allows only lower 48bits of hpmeventX to be
configured via SBI PMU. Currently, the driver masks of the higher
bits but doesn't return an error. This will lead to an additional
SBI call for config matching which should return for an invalid
event error in most of the cases.

However, if a platform(i.e Rocket and sifive cores) implements a
bitmap of all bits in the event encoding this will lead to an
incorrect event being programmed leading to user confusion.

Report the error to the user if higher bits are set during the
event mapping itself to avoid the confusion and save an additional
SBI call.

Suggested-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241212-pmu_event_fixes_v2-v2-3-813e8a4f5962@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Atish Patra 2024-12-12 16:09:34 -08:00 committed by Palmer Dabbelt
parent 2c206cdede
commit 3aff4cdbe5
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1 changed files with 5 additions and 2 deletions
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7
drivers/perf/riscv_pmu_sbi.c
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@ -536,8 +536,11 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
switch (config >> 62) {
case 0:
ret = RISCV_PMU_RAW_EVENT_IDX;
*econfig = config & RISCV_PMU_RAW_EVENT_MASK;
/* Return error any bits [48-63] is set as it is not allowed by the spec */
if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) {
*econfig = config & RISCV_PMU_RAW_EVENT_MASK;
ret = RISCV_PMU_RAW_EVENT_IDX;
}
break;
case 2:
ret = (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16);