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[PATCH] chelsio: use standard CRC routines
Replace driver crc calculation with existing library. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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parent
a7377a50b8
commit
57834ca152
2 changed files with 4 additions and 28 deletions
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@ -2360,6 +2360,7 @@ menu "Ethernet (10000 Mbit)"
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config CHELSIO_T1
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config CHELSIO_T1
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tristate "Chelsio 10Gb Ethernet support"
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tristate "Chelsio 10Gb Ethernet support"
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depends on PCI
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depends on PCI
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select CRC32
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help
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help
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This driver supports Chelsio gigabit and 10-gigabit
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This driver supports Chelsio gigabit and 10-gigabit
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Ethernet cards. More information about adapter features and
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Ethernet cards. More information about adapter features and
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@ -43,6 +43,8 @@
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#include "elmer0.h"
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#include "elmer0.h"
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#include "suni1x10gexp_regs.h"
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#include "suni1x10gexp_regs.h"
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#include <linux/crc32.h>
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#define OFFSET(REG_ADDR) (REG_ADDR << 2)
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#define OFFSET(REG_ADDR) (REG_ADDR << 2)
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/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
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/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
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@ -345,33 +347,6 @@ static int pm3393_set_mtu(struct cmac *cmac, int mtu)
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return 0;
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return 0;
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}
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}
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static u32 calc_crc(u8 *b, int len)
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{
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int i;
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u32 crc = (u32)~0;
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/* calculate crc one bit at a time */
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while (len--) {
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crc ^= *b++;
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for (i = 0; i < 8; i++) {
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if (crc & 0x1)
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crc = (crc >> 1) ^ 0xedb88320;
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else
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crc = (crc >> 1);
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}
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}
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/* reverse bits */
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crc = ((crc >> 4) & 0x0f0f0f0f) | ((crc << 4) & 0xf0f0f0f0);
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crc = ((crc >> 2) & 0x33333333) | ((crc << 2) & 0xcccccccc);
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crc = ((crc >> 1) & 0x55555555) | ((crc << 1) & 0xaaaaaaaa);
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/* swap bytes */
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crc = (crc >> 16) | (crc << 16);
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crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
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return crc;
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}
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static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
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static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
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{
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{
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int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
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int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
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@ -405,7 +380,7 @@ static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
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u16 mc_filter[4] = { 0, };
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u16 mc_filter[4] = { 0, };
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while ((addr = t1_get_next_mcaddr(rm))) {
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while ((addr = t1_get_next_mcaddr(rm))) {
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bit = (calc_crc(addr, ETH_ALEN) >> 23) & 0x3f; /* bit[23:28] */
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bit = (ether_crc(ETH_ALEN, addr) >> 23) & 0x3f; /* bit[23:28] */
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mc_filter[bit >> 4] |= 1 << (bit & 0xf);
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mc_filter[bit >> 4] |= 1 << (bit & 0xf);
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}
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}
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pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
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pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
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