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powerpc/83xx: Split usb.c
usb.c contains three independent parts with no common part. Split it. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> [mpe: Drop usb.o from Makefile to fix build] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/75712b54bf9cb85ab10e47cd2772cd2a098ca895.1692199324.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
d25f01fba7
commit
5951b62ba4
4 changed files with 152 additions and 119 deletions
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@ -2,7 +2,7 @@
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#
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# Makefile for the PowerPC 83xx linux kernel.
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#
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obj-y := misc.o usb.o
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obj-y := misc.o
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obj-$(CONFIG_SUSPEND) += suspend.o suspend-asm.o
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obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mpc8349emitx.o
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obj-$(CONFIG_MPC830x_RDB) += mpc830x_rdb.o
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@ -13,3 +13,6 @@ obj-$(CONFIG_MPC836x_RDK) += mpc836x_rdk.o
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obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o
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obj-$(CONFIG_ASP834x) += asp834x.o
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obj-$(CONFIG_KMETER1) += km83xx.o
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obj-$(CONFIG_PPC_MPC831x) += usb_831x.o
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obj-$(CONFIG_PPC_MPC834x) += usb_834x.o
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obj-$(CONFIG_PPC_MPC837x) += usb_837x.o
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@ -17,81 +17,6 @@
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#include "mpc83xx.h"
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#ifdef CONFIG_PPC_MPC834x
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int __init mpc834x_usb_cfg(void)
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{
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unsigned long sccr, sicrl, sicrh;
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void __iomem *immap;
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struct device_node *np = NULL;
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int port0_is_dr = 0, port1_is_dr = 0;
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const void *prop, *dr_mode;
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immap = ioremap(get_immrbase(), 0x1000);
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if (!immap)
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return -ENOMEM;
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/* Read registers */
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/* Note: DR and MPH must use the same clock setting in SCCR */
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sccr = in_be32(immap + MPC83XX_SCCR_OFFS) & ~MPC83XX_SCCR_USB_MASK;
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sicrl = in_be32(immap + MPC83XX_SICRL_OFFS) & ~MPC834X_SICRL_USB_MASK;
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sicrh = in_be32(immap + MPC83XX_SICRH_OFFS) & ~MPC834X_SICRH_USB_UTMI;
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
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if (np) {
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sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */
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prop = of_get_property(np, "phy_type", NULL);
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port1_is_dr = 1;
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if (prop &&
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(!strcmp(prop, "utmi") || !strcmp(prop, "utmi_wide"))) {
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sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
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sicrh |= MPC834X_SICRH_USB_UTMI;
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port0_is_dr = 1;
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} else if (prop && !strcmp(prop, "serial")) {
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dr_mode = of_get_property(np, "dr_mode", NULL);
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if (dr_mode && !strcmp(dr_mode, "otg")) {
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sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
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port0_is_dr = 1;
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} else {
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sicrl |= MPC834X_SICRL_USB1;
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}
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} else if (prop && !strcmp(prop, "ulpi")) {
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sicrl |= MPC834X_SICRL_USB1;
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} else {
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pr_warn("834x USB PHY type not supported\n");
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}
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of_node_put(np);
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}
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");
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if (np) {
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sccr |= MPC83XX_SCCR_USB_MPHCM_11; /* 1:3 */
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prop = of_get_property(np, "port0", NULL);
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if (prop) {
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if (port0_is_dr)
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pr_warn("834x USB port0 can't be used by both DR and MPH!\n");
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sicrl &= ~MPC834X_SICRL_USB0;
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}
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prop = of_get_property(np, "port1", NULL);
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if (prop) {
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if (port1_is_dr)
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pr_warn("834x USB port1 can't be used by both DR and MPH!\n");
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sicrl &= ~MPC834X_SICRL_USB1;
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}
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of_node_put(np);
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}
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/* Write back */
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out_be32(immap + MPC83XX_SCCR_OFFS, sccr);
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out_be32(immap + MPC83XX_SICRL_OFFS, sicrl);
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out_be32(immap + MPC83XX_SICRH_OFFS, sicrh);
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iounmap(immap);
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return 0;
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}
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#endif /* CONFIG_PPC_MPC834x */
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#ifdef CONFIG_PPC_MPC831x
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int __init mpc831x_usb_cfg(void)
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{
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u32 temp;
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@ -201,46 +126,3 @@ out:
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of_node_put(np);
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return ret;
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}
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#endif /* CONFIG_PPC_MPC831x */
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#ifdef CONFIG_PPC_MPC837x
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int __init mpc837x_usb_cfg(void)
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{
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void __iomem *immap;
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struct device_node *np = NULL;
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const void *prop;
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int ret = 0;
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
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if (!np || !of_device_is_available(np)) {
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of_node_put(np);
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return -ENODEV;
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}
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prop = of_get_property(np, "phy_type", NULL);
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if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) {
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pr_warn("837x USB PHY type not supported\n");
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of_node_put(np);
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return -EINVAL;
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}
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/* Map IMMR space for pin and clock settings */
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immap = ioremap(get_immrbase(), 0x1000);
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if (!immap) {
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of_node_put(np);
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return -ENOMEM;
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}
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/* Configure clock */
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clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
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MPC837X_SCCR_USB_DRCM_11);
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/* Configure pin mux for ULPI/serial */
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clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
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MPC837X_SICRL_USB_ULPI);
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iounmap(immap);
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of_node_put(np);
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return ret;
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}
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#endif /* CONFIG_PPC_MPC837x */
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90
arch/powerpc/platforms/83xx/usb_834x.c
Normal file
90
arch/powerpc/platforms/83xx/usb_834x.c
Normal file
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@ -0,0 +1,90 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Freescale 83xx USB SOC setup code
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*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Author: Li Yang
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc83xx.h"
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int __init mpc834x_usb_cfg(void)
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{
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unsigned long sccr, sicrl, sicrh;
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void __iomem *immap;
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struct device_node *np = NULL;
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int port0_is_dr = 0, port1_is_dr = 0;
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const void *prop, *dr_mode;
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immap = ioremap(get_immrbase(), 0x1000);
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if (!immap)
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return -ENOMEM;
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/* Read registers */
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/* Note: DR and MPH must use the same clock setting in SCCR */
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sccr = in_be32(immap + MPC83XX_SCCR_OFFS) & ~MPC83XX_SCCR_USB_MASK;
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sicrl = in_be32(immap + MPC83XX_SICRL_OFFS) & ~MPC834X_SICRL_USB_MASK;
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sicrh = in_be32(immap + MPC83XX_SICRH_OFFS) & ~MPC834X_SICRH_USB_UTMI;
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
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if (np) {
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sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */
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prop = of_get_property(np, "phy_type", NULL);
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port1_is_dr = 1;
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if (prop &&
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(!strcmp(prop, "utmi") || !strcmp(prop, "utmi_wide"))) {
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sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
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sicrh |= MPC834X_SICRH_USB_UTMI;
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port0_is_dr = 1;
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} else if (prop && !strcmp(prop, "serial")) {
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dr_mode = of_get_property(np, "dr_mode", NULL);
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if (dr_mode && !strcmp(dr_mode, "otg")) {
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sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
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port0_is_dr = 1;
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} else {
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sicrl |= MPC834X_SICRL_USB1;
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}
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} else if (prop && !strcmp(prop, "ulpi")) {
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sicrl |= MPC834X_SICRL_USB1;
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} else {
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pr_warn("834x USB PHY type not supported\n");
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}
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of_node_put(np);
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}
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");
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if (np) {
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sccr |= MPC83XX_SCCR_USB_MPHCM_11; /* 1:3 */
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prop = of_get_property(np, "port0", NULL);
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if (prop) {
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if (port0_is_dr)
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pr_warn("834x USB port0 can't be used by both DR and MPH!\n");
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sicrl &= ~MPC834X_SICRL_USB0;
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}
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prop = of_get_property(np, "port1", NULL);
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if (prop) {
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if (port1_is_dr)
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pr_warn("834x USB port1 can't be used by both DR and MPH!\n");
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sicrl &= ~MPC834X_SICRL_USB1;
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}
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of_node_put(np);
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}
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/* Write back */
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out_be32(immap + MPC83XX_SCCR_OFFS, sccr);
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out_be32(immap + MPC83XX_SICRL_OFFS, sicrl);
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out_be32(immap + MPC83XX_SICRH_OFFS, sicrh);
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iounmap(immap);
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return 0;
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}
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58
arch/powerpc/platforms/83xx/usb_837x.c
Normal file
58
arch/powerpc/platforms/83xx/usb_837x.c
Normal file
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@ -0,0 +1,58 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Freescale 83xx USB SOC setup code
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*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Author: Li Yang
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc83xx.h"
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int __init mpc837x_usb_cfg(void)
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{
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void __iomem *immap;
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struct device_node *np = NULL;
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const void *prop;
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int ret = 0;
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
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if (!np || !of_device_is_available(np)) {
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of_node_put(np);
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return -ENODEV;
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}
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prop = of_get_property(np, "phy_type", NULL);
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if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) {
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pr_warn("837x USB PHY type not supported\n");
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of_node_put(np);
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return -EINVAL;
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}
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/* Map IMMR space for pin and clock settings */
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immap = ioremap(get_immrbase(), 0x1000);
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if (!immap) {
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of_node_put(np);
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return -ENOMEM;
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}
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/* Configure clock */
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clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
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MPC837X_SCCR_USB_DRCM_11);
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/* Configure pin mux for ULPI/serial */
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clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
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MPC837X_SICRL_USB_ULPI);
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iounmap(immap);
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of_node_put(np);
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return ret;
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}
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