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Miscellaneous x86 cleanups and typo fixes, and also the removal

of the "disablelapic" boot parameter.
 
 Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Merge tag 'x86-cleanups-2025-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cleanups from Ingo Molnar:
 "Miscellaneous x86 cleanups and typo fixes, and also the removal of
  the 'disablelapic' boot parameter"

* tag 'x86-cleanups-2025-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/ioapic: Remove a stray tab in the IO-APIC type string
  x86/cpufeatures: Remove "AMD" from the comments to the AMD-specific leaf
  Documentation/kernel-parameters: Fix a typo in kvm.enable_virt_at_load text
  x86/cpu: Fix typo in x86_match_cpu()'s doc
  x86/apic: Remove "disablelapic" cmdline option
  Documentation: Merge x86-specific boot options doc into kernel-parameters.txt
  x86/ioremap: Remove unused size parameter in remapping functions
  x86/ioremap: Simplify setup_data mapping variants
  x86/boot/compressed: Remove unused header includes from kaslr.c
This commit is contained in:
Linus Torvalds 2025-01-21 11:15:29 -08:00
commit 858df1de21
14 changed files with 278 additions and 435 deletions

View file

@ -194,8 +194,6 @@ is applicable::
WDT Watchdog support is enabled. WDT Watchdog support is enabled.
X86-32 X86-32, aka i386 architecture is enabled. X86-32 X86-32, aka i386 architecture is enabled.
X86-64 X86-64 architecture is enabled. X86-64 X86-64 architecture is enabled.
More X86-64 boot options can be found in
Documentation/arch/x86/x86_64/boot-options.rst.
X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64) X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64)
X86_UV SGI UV support is enabled. X86_UV SGI UV support is enabled.
XEN Xen support is enabled XEN Xen support is enabled
@ -213,7 +211,6 @@ Do not modify the syntax of boot loader parameters without extreme
need or coordination with <Documentation/arch/x86/boot.rst>. need or coordination with <Documentation/arch/x86/boot.rst>.
There are also arch-specific kernel-parameters not documented here. There are also arch-specific kernel-parameters not documented here.
See for example <Documentation/arch/x86/x86_64/boot-options.rst>.
Note that ALL kernel parameters listed below are CASE SENSITIVE, and that Note that ALL kernel parameters listed below are CASE SENSITIVE, and that
a trailing = on the name of any parameter states that that parameter will a trailing = on the name of any parameter states that that parameter will

View file

@ -21,6 +21,10 @@
strictly ACPI specification compliant. strictly ACPI specification compliant.
rsdt -- prefer RSDT over (default) XSDT rsdt -- prefer RSDT over (default) XSDT
copy_dsdt -- copy DSDT to memory copy_dsdt -- copy DSDT to memory
nocmcff -- Disable firmware first mode for corrected
errors. This disables parsing the HEST CMC error
source to check if firmware has set the FF flag. This
may result in duplicate corrected error reports.
nospcr -- disable console in ACPI SPCR table as nospcr -- disable console in ACPI SPCR table as
default _serial_ console on ARM64 default _serial_ console on ARM64
For ARM64, ONLY "acpi=off", "acpi=on", "acpi=force" or For ARM64, ONLY "acpi=off", "acpi=on", "acpi=force" or
@ -405,6 +409,8 @@
not play well with APC CPU idle - disable it if you have not play well with APC CPU idle - disable it if you have
APC and your system crashes randomly. APC and your system crashes randomly.
apic [APIC,X86-64] Use IO-APIC. Default.
apic= [APIC,X86,EARLY] Advanced Programmable Interrupt Controller apic= [APIC,X86,EARLY] Advanced Programmable Interrupt Controller
Change the output verbosity while booting Change the output verbosity while booting
Format: { quiet (default) | verbose | debug } Format: { quiet (default) | verbose | debug }
@ -424,6 +430,10 @@
useful so that a dump capture kernel won't be useful so that a dump capture kernel won't be
shot down by NMI shot down by NMI
apicpmtimer Do APIC timer calibration using the pmtimer. Implies
apicmaintimer. Useful when your PIT timer is totally
broken.
autoconf= [IPV6] autoconf= [IPV6]
See Documentation/networking/ipv6.rst. See Documentation/networking/ipv6.rst.
@ -1726,6 +1736,8 @@
off: Disable GDS mitigation. off: Disable GDS mitigation.
gbpages [X86] Use GB pages for kernel direct mappings.
gcov_persist= [GCOV] When non-zero (default), profiling data for gcov_persist= [GCOV] When non-zero (default), profiling data for
kernel modules is saved and remains accessible via kernel modules is saved and remains accessible via
debugfs, even when the module is unloaded/reloaded. debugfs, even when the module is unloaded/reloaded.
@ -2008,12 +2020,21 @@
idle= [X86,EARLY] idle= [X86,EARLY]
Format: idle=poll, idle=halt, idle=nomwait Format: idle=poll, idle=halt, idle=nomwait
Poll forces a polling idle loop that can slightly
improve the performance of waking up a idle CPU, but idle=poll: Don't do power saving in the idle loop
will use a lot of power and make the system run hot. using HLT, but poll for rescheduling event. This will
Not recommended. make the CPUs eat a lot more power, but may be useful
to get slightly better performance in multiprocessor
benchmarks. It also makes some profiling using
performance counters more accurate. Please note that
on systems with MONITOR/MWAIT support (like Intel
EM64T CPUs) this option has no performance advantage
over the normal idle loop. It may also interact badly
with hyperthreading.
idle=halt: Halt is forced to be used for CPU idle. idle=halt: Halt is forced to be used for CPU idle.
In such case C2/C3 won't be used again. In such case C2/C3 won't be used again.
idle=nomwait: Disable mwait for CPU C-states idle=nomwait: Disable mwait for CPU C-states
idxd.sva= [HW] idxd.sva= [HW]
@ -2311,20 +2332,73 @@
relaxed relaxed
iommu= [X86,EARLY] iommu= [X86,EARLY]
off off
Don't initialize and use any kind of IOMMU.
force force
Force the use of the hardware IOMMU even when
it is not actually needed (e.g. because < 3 GB
memory).
noforce noforce
Don't force hardware IOMMU usage when it is not
needed. (default).
biomerge biomerge
panic panic
nopanic nopanic
merge merge
nomerge nomerge
soft soft
pt [X86] Use software bounce buffering (SWIOTLB) (default for
nopt [X86] Intel machines). This can be used to prevent the usage
nobypass [PPC/POWERNV] of an available hardware IOMMU.
[X86]
pt
[X86]
nopt
[PPC/POWERNV]
nobypass
Disable IOMMU bypass, using IOMMU for PCI devices. Disable IOMMU bypass, using IOMMU for PCI devices.
[X86]
AMD Gart HW IOMMU-specific options:
<size>
Set the size of the remapping area in bytes.
allowed
Overwrite iommu off workarounds for specific chipsets
fullflush
Flush IOMMU on each allocation (default).
nofullflush
Don't use IOMMU fullflush.
memaper[=<order>]
Allocate an own aperture over RAM with size
32MB<<order. (default: order=1, i.e. 64MB)
merge
Do scatter-gather (SG) merging. Implies "force"
(experimental).
nomerge
Don't do scatter-gather (SG) merging.
noaperture
Ask the IOMMU not to touch the aperture for AGP.
noagp
Don't initialize the AGP driver and use full aperture.
panic
Always panic when IOMMU overflows.
iommu.forcedac= [ARM64,X86,EARLY] Control IOVA allocation for PCI devices. iommu.forcedac= [ARM64,X86,EARLY] Control IOVA allocation for PCI devices.
Format: { "0" | "1" } Format: { "0" | "1" }
0 - Try to allocate a 32-bit DMA address first, before 0 - Try to allocate a 32-bit DMA address first, before
@ -2695,7 +2769,7 @@
VMs, i.e. on the 0=>1 and 1=>0 transitions of the VMs, i.e. on the 0=>1 and 1=>0 transitions of the
number of VMs. number of VMs.
Enabling virtualization at module lode avoids potential Enabling virtualization at module load avoids potential
latency for creation of the 0=>1 VM, as KVM serializes latency for creation of the 0=>1 VM, as KVM serializes
virtualization enabling across all online CPUs. The virtualization enabling across all online CPUs. The
"cost" of enabling virtualization when KVM is loaded, "cost" of enabling virtualization when KVM is loaded,
@ -3259,9 +3333,77 @@
devices can be requested on-demand with the devices can be requested on-demand with the
/dev/loop-control interface. /dev/loop-control interface.
mce [X86-32] Machine Check Exception mce= [X86-{32,64}]
Please see Documentation/arch/x86/x86_64/machinecheck.rst for sysfs runtime tunables.
off
disable machine check
no_cmci
disable CMCI(Corrected Machine Check Interrupt) that
Intel processor supports. Usually this disablement is
not recommended, but it might be handy if your
hardware is misbehaving.
Note that you'll get more problems without CMCI than
with due to the shared banks, i.e. you might get
duplicated error logs.
dont_log_ce
don't make logs for corrected errors. All events
reported as corrected are silently cleared by OS. This
option will be useful if you have no interest in any
of corrected errors.
ignore_ce
disable features for corrected errors, e.g.
polling timer and CMCI. All events reported as
corrected are not cleared by OS and remained in its
error banks.
Usually this disablement is not recommended, however
if there is an agent checking/clearing corrected
errors (e.g. BIOS or hardware monitoring
applications), conflicting with OS's error handling,
and you cannot deactivate the agent, then this option
will be a help.
no_lmce
do not opt-in to Local MCE delivery. Use legacy method
to broadcast MCEs.
bootlog
enable logging of machine checks left over from
booting. Disabled by default on AMD Fam10h and older
because some BIOS leave bogus ones.
If your BIOS doesn't do that it's a good idea to
enable though to make sure you log even machine check
events that result in a reboot. On Intel systems it is
enabled by default.
nobootlog
disable boot machine check logging.
monarchtimeout (number)
sets the time in us to wait for other CPUs on machine
checks. 0 to disable.
bios_cmci_threshold
don't overwrite the bios-set CMCI threshold. This boot
option prevents Linux from overwriting the CMCI
threshold set by the bios. Without this option, Linux
always sets the CMCI threshold to 1. Enabling this may
make memory predictive failure analysis less effective
if the bios sets thresholds for memory errors since we
will not see details for all errors.
recovery
force-enable recoverable machine check code paths
Everything else is in sysfs now.
mce=option [X86-64] See Documentation/arch/x86/x86_64/boot-options.rst
md= [HW] RAID subsystems devices and level md= [HW] RAID subsystems devices and level
See Documentation/admin-guide/md.rst. See Documentation/admin-guide/md.rst.
@ -3887,6 +4029,8 @@
noapic [SMP,APIC,EARLY] Tells the kernel to not make use of any noapic [SMP,APIC,EARLY] Tells the kernel to not make use of any
IOAPICs that may be present in the system. IOAPICs that may be present in the system.
noapictimer [APIC,X86] Don't set up the APIC timer
noautogroup Disable scheduler automatic task group creation. noautogroup Disable scheduler automatic task group creation.
nocache [ARM,EARLY] nocache [ARM,EARLY]
@ -3934,6 +4078,8 @@
register save and restore. The kernel will only save register save and restore. The kernel will only save
legacy floating-point registers on task switch. legacy floating-point registers on task switch.
nogbpages [X86] Do not use GB pages for kernel direct mappings.
no_hash_pointers no_hash_pointers
[KNL,EARLY] [KNL,EARLY]
Force pointers printed to the console or buffers to be Force pointers printed to the console or buffers to be
@ -3960,6 +4106,8 @@
the impact of the sleep instructions. This is also the impact of the sleep instructions. This is also
useful when using JTAG debugger. useful when using JTAG debugger.
nohpet [X86] Don't use the HPET timer.
nohugeiomap [KNL,X86,PPC,ARM64,EARLY] Disable kernel huge I/O mappings. nohugeiomap [KNL,X86,PPC,ARM64,EARLY] Disable kernel huge I/O mappings.
nohugevmalloc [KNL,X86,PPC,ARM64,EARLY] Disable kernel huge vmalloc mappings. nohugevmalloc [KNL,X86,PPC,ARM64,EARLY] Disable kernel huge vmalloc mappings.
@ -4111,8 +4259,10 @@
nosync [HW,M68K] Disables sync negotiation for all devices. nosync [HW,M68K] Disables sync negotiation for all devices.
no_timer_check [X86,APIC] Disables the code which tests for no_timer_check [X86,APIC] Disables the code which tests for broken
broken timer IRQ sources. timer IRQ sources, i.e., the IO-APIC timer. This can
work around problems with incorrect timer
initialization on some boards.
no_uaccess_flush no_uaccess_flush
[PPC,EARLY] Don't flush the L1-D cache after accessing user data. [PPC,EARLY] Don't flush the L1-D cache after accessing user data.
@ -4192,6 +4342,11 @@
If given as an integer followed by 'U', it will If given as an integer followed by 'U', it will
divide each physical node into N emulated nodes. divide each physical node into N emulated nodes.
numa=noacpi [X86] Don't parse the SRAT table for NUMA setup
numa=nohmat [X86] Don't parse the HMAT table for NUMA setup, or
soft-reserved memory partitioning.
numa_balancing= [KNL,ARM64,PPC,RISCV,S390,X86] Enable or disable automatic numa_balancing= [KNL,ARM64,PPC,RISCV,S390,X86] Enable or disable automatic
NUMA balancing. NUMA balancing.
Allowed values are enable and disable Allowed values are enable and disable
@ -5715,6 +5870,55 @@
reboot_cpu is s[mp]#### with #### being the processor reboot_cpu is s[mp]#### with #### being the processor
to be used for rebooting. to be used for rebooting.
acpi
Use the ACPI RESET_REG in the FADT. If ACPI is not
configured or the ACPI reset does not work, the reboot
path attempts the reset using the keyboard controller.
bios
Use the CPU reboot vector for warm reset
cold
Set the cold reboot flag
default
There are some built-in platform specific "quirks"
- you may see: "reboot: <name> series board detected.
Selecting <type> for reboots." In the case where you
think the quirk is in error (e.g. you have newer BIOS,
or newer board) using this option will ignore the
built-in quirk table, and use the generic default
reboot actions.
efi
Use efi reset_system runtime service. If EFI is not
configured or the EFI reset does not work, the reboot
path attempts the reset using the keyboard controller.
force
Don't stop other CPUs on reboot. This can make reboot
more reliable in some cases.
kbd
Use the keyboard controller. cold reset (default)
pci
Use a write to the PCI config space register 0xcf9 to
trigger reboot.
triple
Force a triple fault (init)
warm
Don't set the cold reboot flag
Using warm reset will be much faster especially on big
memory systems because the BIOS will not go through
the memory check. Disadvantage is that not all
hardware will be completely reinitialized on reboot so
there may be boot problems on some systems.
refscale.holdoff= [KNL] refscale.holdoff= [KNL]
Set test-start holdoff period. The purpose of Set test-start holdoff period. The purpose of
this parameter is to delay the start of the this parameter is to delay the start of the
@ -6106,7 +6310,16 @@
serialnumber [BUGS=X86-32] serialnumber [BUGS=X86-32]
sev=option[,option...] [X86-64] See Documentation/arch/x86/x86_64/boot-options.rst sev=option[,option...] [X86-64]
debug
Enable debug messages.
nosnp
Do not enable SEV-SNP (applies to host/hypervisor
only). Setting 'nosnp' avoids the RMP check overhead
in memory accesses when users do not want to run
SEV-SNP guests.
shapers= [NET] shapers= [NET]
Maximal number of shapers. Maximal number of shapers.

View file

@ -1,312 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0
===========================
AMD64 Specific Boot Options
===========================
There are many others (usually documented in driver documentation), but
only the AMD64 specific ones are listed here.
Machine check
=============
Please see Documentation/arch/x86/x86_64/machinecheck.rst for sysfs runtime tunables.
mce=off
Disable machine check
mce=no_cmci
Disable CMCI(Corrected Machine Check Interrupt) that
Intel processor supports. Usually this disablement is
not recommended, but it might be handy if your hardware
is misbehaving.
Note that you'll get more problems without CMCI than with
due to the shared banks, i.e. you might get duplicated
error logs.
mce=dont_log_ce
Don't make logs for corrected errors. All events reported
as corrected are silently cleared by OS.
This option will be useful if you have no interest in any
of corrected errors.
mce=ignore_ce
Disable features for corrected errors, e.g. polling timer
and CMCI. All events reported as corrected are not cleared
by OS and remained in its error banks.
Usually this disablement is not recommended, however if
there is an agent checking/clearing corrected errors
(e.g. BIOS or hardware monitoring applications), conflicting
with OS's error handling, and you cannot deactivate the agent,
then this option will be a help.
mce=no_lmce
Do not opt-in to Local MCE delivery. Use legacy method
to broadcast MCEs.
mce=bootlog
Enable logging of machine checks left over from booting.
Disabled by default on AMD Fam10h and older because some BIOS
leave bogus ones.
If your BIOS doesn't do that it's a good idea to enable though
to make sure you log even machine check events that result
in a reboot. On Intel systems it is enabled by default.
mce=nobootlog
Disable boot machine check logging.
mce=monarchtimeout (number)
monarchtimeout:
Sets the time in us to wait for other CPUs on machine checks. 0
to disable.
mce=bios_cmci_threshold
Don't overwrite the bios-set CMCI threshold. This boot option
prevents Linux from overwriting the CMCI threshold set by the
bios. Without this option, Linux always sets the CMCI
threshold to 1. Enabling this may make memory predictive failure
analysis less effective if the bios sets thresholds for memory
errors since we will not see details for all errors.
mce=recovery
Force-enable recoverable machine check code paths
nomce (for compatibility with i386)
same as mce=off
Everything else is in sysfs now.
APICs
=====
apic
Use IO-APIC. Default
noapic
Don't use the IO-APIC.
disableapic
Don't use the local APIC
nolapic
Don't use the local APIC (alias for i386 compatibility)
pirq=...
See Documentation/arch/x86/i386/IO-APIC.rst
noapictimer
Don't set up the APIC timer
no_timer_check
Don't check the IO-APIC timer. This can work around
problems with incorrect timer initialization on some boards.
apicpmtimer
Do APIC timer calibration using the pmtimer. Implies
apicmaintimer. Useful when your PIT timer is totally broken.
Timing
======
notsc
Deprecated, use tsc=unstable instead.
nohpet
Don't use the HPET timer.
Idle loop
=========
idle=poll
Don't do power saving in the idle loop using HLT, but poll for rescheduling
event. This will make the CPUs eat a lot more power, but may be useful
to get slightly better performance in multiprocessor benchmarks. It also
makes some profiling using performance counters more accurate.
Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
CPUs) this option has no performance advantage over the normal idle loop.
It may also interact badly with hyperthreading.
Rebooting
=========
reboot=b[ios] | t[riple] | k[bd] | a[cpi] | e[fi] | p[ci] [, [w]arm | [c]old]
bios
Use the CPU reboot vector for warm reset
warm
Don't set the cold reboot flag
cold
Set the cold reboot flag
triple
Force a triple fault (init)
kbd
Use the keyboard controller. cold reset (default)
acpi
Use the ACPI RESET_REG in the FADT. If ACPI is not configured or
the ACPI reset does not work, the reboot path attempts the reset
using the keyboard controller.
efi
Use efi reset_system runtime service. If EFI is not configured or
the EFI reset does not work, the reboot path attempts the reset using
the keyboard controller.
pci
Use a write to the PCI config space register 0xcf9 to trigger reboot.
Using warm reset will be much faster especially on big memory
systems because the BIOS will not go through the memory check.
Disadvantage is that not all hardware will be completely reinitialized
on reboot so there may be boot problems on some systems.
reboot=force
Don't stop other CPUs on reboot. This can make reboot more reliable
in some cases.
reboot=default
There are some built-in platform specific "quirks" - you may see:
"reboot: <name> series board detected. Selecting <type> for reboots."
In the case where you think the quirk is in error (e.g. you have
newer BIOS, or newer board) using this option will ignore the built-in
quirk table, and use the generic default reboot actions.
NUMA
====
numa=off
Only set up a single NUMA node spanning all memory.
numa=noacpi
Don't parse the SRAT table for NUMA setup
numa=nohmat
Don't parse the HMAT table for NUMA setup, or soft-reserved memory
partitioning.
ACPI
====
acpi=off
Don't enable ACPI
acpi=ht
Use ACPI boot table parsing, but don't enable ACPI interpreter
acpi=force
Force ACPI on (currently not needed)
acpi=strict
Disable out of spec ACPI workarounds.
acpi_sci={edge,level,high,low}
Set up ACPI SCI interrupt.
acpi=noirq
Don't route interrupts
acpi=nocmcff
Disable firmware first mode for corrected errors. This
disables parsing the HEST CMC error source to check if
firmware has set the FF flag. This may result in
duplicate corrected error reports.
PCI
===
pci=off
Don't use PCI
pci=conf1
Use conf1 access.
pci=conf2
Use conf2 access.
pci=rom
Assign ROMs.
pci=assign-busses
Assign busses
pci=irqmask=MASK
Set PCI interrupt mask to MASK
pci=lastbus=NUMBER
Scan up to NUMBER busses, no matter what the mptable says.
pci=noacpi
Don't use ACPI to set up PCI interrupt routing.
IOMMU (input/output memory management unit)
===========================================
Multiple x86-64 PCI-DMA mapping implementations exist, for example:
1. <kernel/dma/direct.c>: use no hardware/software IOMMU at all
(e.g. because you have < 3 GB memory).
Kernel boot message: "PCI-DMA: Disabling IOMMU"
2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU.
Kernel boot message: "PCI-DMA: using GART IOMMU"
3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
e.g. if there is no hardware IOMMU in the system and it is need because
you have >3GB memory or told the kernel to us it (iommu=soft))
Kernel boot message: "PCI-DMA: Using software bounce buffering
for IO (SWIOTLB)"
::
iommu=[<size>][,noagp][,off][,force][,noforce]
[,memaper[=<order>]][,merge][,fullflush][,nomerge]
[,noaperture]
General iommu options:
off
Don't initialize and use any kind of IOMMU.
noforce
Don't force hardware IOMMU usage when it is not needed. (default).
force
Force the use of the hardware IOMMU even when it is
not actually needed (e.g. because < 3 GB memory).
soft
Use software bounce buffering (SWIOTLB) (default for
Intel machines). This can be used to prevent the usage
of an available hardware IOMMU.
iommu options only relevant to the AMD GART hardware IOMMU:
<size>
Set the size of the remapping area in bytes.
allowed
Overwrite iommu off workarounds for specific chipsets.
fullflush
Flush IOMMU on each allocation (default).
nofullflush
Don't use IOMMU fullflush.
memaper[=<order>]
Allocate an own aperture over RAM with size 32MB<<order.
(default: order=1, i.e. 64MB)
merge
Do scatter-gather (SG) merging. Implies "force" (experimental).
nomerge
Don't do scatter-gather (SG) merging.
noaperture
Ask the IOMMU not to touch the aperture for AGP.
noagp
Don't initialize the AGP driver and use full aperture.
panic
Always panic when IOMMU overflows.
iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
implementation:
swiotlb=<slots>[,force,noforce]
<slots>
Prereserve that many 2K slots for the software IO bounce buffering.
force
Force all IO through the software TLB.
noforce
Do not initialize the software TLB.
Miscellaneous
=============
nogbpages
Do not use GB pages for kernel direct mappings.
gbpages
Use GB pages for kernel direct mappings.
AMD SEV (Secure Encrypted Virtualization)
=========================================
Options relating to AMD SEV, specified via the following format:
::
sev=option1[,option2]
The available options are:
debug
Enable debug messages.
nosnp
Do not enable SEV-SNP (applies to host/hypervisor only). Setting
'nosnp' avoids the RMP check overhead in memory accesses when
users do not want to run SEV-SNP guests.

View file

@ -18,7 +18,7 @@ For more information on the features of cpusets, see
Documentation/admin-guide/cgroup-v1/cpusets.rst. Documentation/admin-guide/cgroup-v1/cpusets.rst.
There are a number of different configurations you can use for your needs. For There are a number of different configurations you can use for your needs. For
more information on the numa=fake command line option and its various ways of more information on the numa=fake command line option and its various ways of
configuring fake nodes, see Documentation/arch/x86/x86_64/boot-options.rst. configuring fake nodes, see Documentation/admin-guide/kernel-parameters.txt
For the purposes of this introduction, we'll assume a very primitive NUMA For the purposes of this introduction, we'll assume a very primitive NUMA
emulation setup of "numa=fake=4*512,". This will split our system memory into emulation setup of "numa=fake=4*512,". This will split our system memory into

View file

@ -7,7 +7,6 @@ x86_64 Support
.. toctree:: .. toctree::
:maxdepth: 2 :maxdepth: 2
boot-options
uefi uefi
mm mm
5level-paging 5level-paging

View file

@ -97,7 +97,7 @@ config IOMMU_DEBUG
code. When you use it make sure you have a big enough code. When you use it make sure you have a big enough
IOMMU/AGP aperture. Most of the options enabled by this can IOMMU/AGP aperture. Most of the options enabled by this can
be set more finegrained using the iommu= command line be set more finegrained using the iommu= command line
options. See Documentation/arch/x86/x86_64/boot-options.rst for more options. See Documentation/admin-guide/kernel-parameters.txt for more
details. details.
config IOMMU_LEAK config IOMMU_LEAK

View file

@ -25,10 +25,6 @@
#include "efi.h" #include "efi.h"
#include <generated/compile.h> #include <generated/compile.h>
#include <linux/module.h>
#include <linux/uts.h>
#include <linux/utsname.h>
#include <linux/ctype.h>
#include <generated/utsversion.h> #include <generated/utsversion.h>
#include <generated/utsrelease.h> #include <generated/utsrelease.h>

View file

@ -443,14 +443,14 @@
#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* Speculative Store Bypass Disable */ #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* Speculative Store Bypass Disable */
/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */ /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
#define X86_FEATURE_SME (19*32+ 0) /* "sme" AMD Secure Memory Encryption */ #define X86_FEATURE_SME (19*32+ 0) /* "sme" Secure Memory Encryption */
#define X86_FEATURE_SEV (19*32+ 1) /* "sev" AMD Secure Encrypted Virtualization */ #define X86_FEATURE_SEV (19*32+ 1) /* "sev" Secure Encrypted Virtualization */
#define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* VM Page Flush MSR is supported */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* VM Page Flush MSR is supported */
#define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" AMD Secure Encrypted Virtualization - Encrypted State */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */
#define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */
#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */
#define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache coherency */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */
#define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
#define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */ #define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */
#define X86_FEATURE_SEGMENTED_RMP (19*32+23) /* Segmented RMP support */ #define X86_FEATURE_SEGMENTED_RMP (19*32+23) /* Segmented RMP support */
#define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */

View file

@ -2582,19 +2582,12 @@ int apic_is_clustered_box(void)
/* /*
* APIC command line parameters * APIC command line parameters
*/ */
static int __init setup_disableapic(char *arg) static int __init setup_nolapic(char *arg)
{ {
apic_is_disabled = true; apic_is_disabled = true;
setup_clear_cpu_cap(X86_FEATURE_APIC); setup_clear_cpu_cap(X86_FEATURE_APIC);
return 0; return 0;
} }
early_param("disableapic", setup_disableapic);
/* same as disableapic, for compatibility */
static int __init setup_nolapic(char *arg)
{
return setup_disableapic(arg);
}
early_param("nolapic", setup_nolapic); early_param("nolapic", setup_nolapic);
static int __init parse_lapic_timer_c2_ok(char *arg) static int __init parse_lapic_timer_c2_ok(char *arg)

View file

@ -1165,7 +1165,7 @@ static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
(entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero); (entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero);
} else { } else {
apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf, apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf,
entry.dest_mode_logical ? "logical " : "physic al", entry.dest_mode_logical ? "logical " : "physical",
entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode); entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode);
} }
} }

View file

@ -6,7 +6,7 @@
#include <linux/slab.h> #include <linux/slab.h>
/** /**
* x86_match_cpu - match current CPU again an array of x86_cpu_ids * x86_match_cpu - match current CPU against an array of x86_cpu_ids
* @match: Pointer to array of x86_cpu_ids. Last entry terminated with * @match: Pointer to array of x86_cpu_ids. Last entry terminated with
* {}. * {}.
* *

View file

@ -428,7 +428,7 @@ void __init topology_apply_cmdline_limits_early(void)
{ {
unsigned int possible = nr_cpu_ids; unsigned int possible = nr_cpu_ids;
/* 'maxcpus=0' 'nosmp' 'nolapic' 'disableapic' */ /* 'maxcpus=0' 'nosmp' 'nolapic' */
if (!setup_max_cpus || apic_is_disabled) if (!setup_max_cpus || apic_is_disabled)
possible = 1; possible = 1;

View file

@ -108,10 +108,6 @@ void __init pci_iommu_alloc(void)
swiotlb_init(x86_swiotlb_enable, x86_swiotlb_flags); swiotlb_init(x86_swiotlb_enable, x86_swiotlb_flags);
} }
/*
* See <Documentation/arch/x86/x86_64/boot-options.rst> for the iommu kernel
* parameter documentation.
*/
static __init int iommu_setup(char *p) static __init int iommu_setup(char *p)
{ {
iommu_merge = 1; iommu_merge = 1;

View file

@ -593,8 +593,7 @@ static bool memremap_should_map_decrypted(resource_size_t phys_addr,
* Examine the physical address to determine if it is EFI data. Check * Examine the physical address to determine if it is EFI data. Check
* it against the boot params structure and EFI tables and memory types. * it against the boot params structure and EFI tables and memory types.
*/ */
static bool memremap_is_efi_data(resource_size_t phys_addr, static bool memremap_is_efi_data(resource_size_t phys_addr)
unsigned long size)
{ {
u64 paddr; u64 paddr;
@ -632,71 +631,9 @@ static bool memremap_is_efi_data(resource_size_t phys_addr,
* Examine the physical address to determine if it is boot data by checking * Examine the physical address to determine if it is boot data by checking
* it against the boot params setup_data chain. * it against the boot params setup_data chain.
*/ */
static bool memremap_is_setup_data(resource_size_t phys_addr, static bool __ref __memremap_is_setup_data(resource_size_t phys_addr, bool early)
unsigned long size)
{
struct setup_indirect *indirect;
struct setup_data *data;
u64 paddr, paddr_next;
paddr = boot_params.hdr.setup_data;
while (paddr) {
unsigned int len;
if (phys_addr == paddr)
return true;
data = memremap(paddr, sizeof(*data),
MEMREMAP_WB | MEMREMAP_DEC);
if (!data) {
pr_warn("failed to memremap setup_data entry\n");
return false;
}
paddr_next = data->next;
len = data->len;
if ((phys_addr > paddr) &&
(phys_addr < (paddr + sizeof(struct setup_data) + len))) {
memunmap(data);
return true;
}
if (data->type == SETUP_INDIRECT) {
memunmap(data);
data = memremap(paddr, sizeof(*data) + len,
MEMREMAP_WB | MEMREMAP_DEC);
if (!data) {
pr_warn("failed to memremap indirect setup_data\n");
return false;
}
indirect = (struct setup_indirect *)data->data;
if (indirect->type != SETUP_INDIRECT) {
paddr = indirect->addr;
len = indirect->len;
}
}
memunmap(data);
if ((phys_addr > paddr) && (phys_addr < (paddr + len)))
return true;
paddr = paddr_next;
}
return false;
}
/*
* Examine the physical address to determine if it is boot data by checking
* it against the boot params setup_data chain (early boot version).
*/
static bool __init early_memremap_is_setup_data(resource_size_t phys_addr,
unsigned long size)
{ {
unsigned int setup_data_sz = sizeof(struct setup_data);
struct setup_indirect *indirect; struct setup_indirect *indirect;
struct setup_data *data; struct setup_data *data;
u64 paddr, paddr_next; u64 paddr, paddr_next;
@ -708,29 +645,40 @@ static bool __init early_memremap_is_setup_data(resource_size_t phys_addr,
if (phys_addr == paddr) if (phys_addr == paddr)
return true; return true;
data = early_memremap_decrypted(paddr, sizeof(*data)); if (early)
data = early_memremap_decrypted(paddr, setup_data_sz);
else
data = memremap(paddr, setup_data_sz, MEMREMAP_WB | MEMREMAP_DEC);
if (!data) { if (!data) {
pr_warn("failed to early memremap setup_data entry\n"); pr_warn("failed to remap setup_data entry\n");
return false; return false;
} }
size = sizeof(*data); size = setup_data_sz;
paddr_next = data->next; paddr_next = data->next;
len = data->len; len = data->len;
if ((phys_addr > paddr) && if ((phys_addr > paddr) &&
(phys_addr < (paddr + sizeof(struct setup_data) + len))) { (phys_addr < (paddr + setup_data_sz + len))) {
early_memunmap(data, sizeof(*data)); if (early)
early_memunmap(data, setup_data_sz);
else
memunmap(data);
return true; return true;
} }
if (data->type == SETUP_INDIRECT) { if (data->type == SETUP_INDIRECT) {
size += len; size += len;
early_memunmap(data, sizeof(*data)); if (early) {
data = early_memremap_decrypted(paddr, size); early_memunmap(data, setup_data_sz);
data = early_memremap_decrypted(paddr, size);
} else {
memunmap(data);
data = memremap(paddr, size, MEMREMAP_WB | MEMREMAP_DEC);
}
if (!data) { if (!data) {
pr_warn("failed to early memremap indirect setup_data\n"); pr_warn("failed to remap indirect setup_data\n");
return false; return false;
} }
@ -742,7 +690,10 @@ static bool __init early_memremap_is_setup_data(resource_size_t phys_addr,
} }
} }
early_memunmap(data, size); if (early)
early_memunmap(data, size);
else
memunmap(data);
if ((phys_addr > paddr) && (phys_addr < (paddr + len))) if ((phys_addr > paddr) && (phys_addr < (paddr + len)))
return true; return true;
@ -753,6 +704,16 @@ static bool __init early_memremap_is_setup_data(resource_size_t phys_addr,
return false; return false;
} }
static bool memremap_is_setup_data(resource_size_t phys_addr)
{
return __memremap_is_setup_data(phys_addr, false);
}
static bool __init early_memremap_is_setup_data(resource_size_t phys_addr)
{
return __memremap_is_setup_data(phys_addr, true);
}
/* /*
* Architecture function to determine if RAM remap is allowed. By default, a * Architecture function to determine if RAM remap is allowed. By default, a
* RAM remap will map the data as encrypted. Determine if a RAM remap should * RAM remap will map the data as encrypted. Determine if a RAM remap should
@ -771,8 +732,8 @@ bool arch_memremap_can_ram_remap(resource_size_t phys_addr, unsigned long size,
return false; return false;
if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) {
if (memremap_is_setup_data(phys_addr, size) || if (memremap_is_setup_data(phys_addr) ||
memremap_is_efi_data(phys_addr, size)) memremap_is_efi_data(phys_addr))
return false; return false;
} }
@ -797,8 +758,8 @@ pgprot_t __init early_memremap_pgprot_adjust(resource_size_t phys_addr,
encrypted_prot = true; encrypted_prot = true;
if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) {
if (early_memremap_is_setup_data(phys_addr, size) || if (early_memremap_is_setup_data(phys_addr) ||
memremap_is_efi_data(phys_addr, size)) memremap_is_efi_data(phys_addr))
encrypted_prot = false; encrypted_prot = false;
} }