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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

Merge in late fixes to prepare for the 6.6 net-next PR.

No conflicts.

Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni 2023-08-29 07:44:56 +02:00
commit c873512ef3
23 changed files with 161 additions and 70 deletions

View file

@ -20,7 +20,7 @@ which is at a different MDIO base address in different switch families.
6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321, 6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
6341, 6350, 6351, 6352 6341, 6350, 6351, 6352
- "marvell,mv88e6190" : Switch has base address 0x00. Use with models: - "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
6163, 6190, 6190X, 6191, 6290, 6390, 6390X 6190, 6190X, 6191, 6290, 6361, 6390, 6390X
- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model: - "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
6220, 6250 6220, 6250

View file

@ -464,7 +464,7 @@ static void arcnet_reply_tasklet(struct tasklet_struct *t)
ret = sock_queue_err_skb(sk, ackskb); ret = sock_queue_err_skb(sk, ackskb);
if (ret) if (ret)
kfree_skb(ackskb); dev_kfree_skb_irq(ackskb);
local_irq_enable(); local_irq_enable();
}; };

View file

@ -464,7 +464,8 @@ void pdsc_teardown(struct pdsc *pdsc, bool removing)
{ {
int i; int i;
pdsc_devcmd_reset(pdsc); if (!pdsc->pdev->is_virtfn)
pdsc_devcmd_reset(pdsc);
pdsc_qcq_free(pdsc, &pdsc->notifyqcq); pdsc_qcq_free(pdsc, &pdsc->notifyqcq);
pdsc_qcq_free(pdsc, &pdsc->adminqcq); pdsc_qcq_free(pdsc, &pdsc->adminqcq);
@ -524,7 +525,8 @@ static void pdsc_fw_down(struct pdsc *pdsc)
} }
/* Notify clients of fw_down */ /* Notify clients of fw_down */
devlink_health_report(pdsc->fw_reporter, "FW down reported", pdsc); if (pdsc->fw_reporter)
devlink_health_report(pdsc->fw_reporter, "FW down reported", pdsc);
pdsc_notify(PDS_EVENT_RESET, &reset_event); pdsc_notify(PDS_EVENT_RESET, &reset_event);
pdsc_stop(pdsc); pdsc_stop(pdsc);
@ -554,8 +556,9 @@ static void pdsc_fw_up(struct pdsc *pdsc)
/* Notify clients of fw_up */ /* Notify clients of fw_up */
pdsc->fw_recoveries++; pdsc->fw_recoveries++;
devlink_health_reporter_state_update(pdsc->fw_reporter, if (pdsc->fw_reporter)
DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); devlink_health_reporter_state_update(pdsc->fw_reporter,
DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
pdsc_notify(PDS_EVENT_RESET, &reset_event); pdsc_notify(PDS_EVENT_RESET, &reset_event);
return; return;

View file

@ -121,7 +121,7 @@ static const char *pdsc_devcmd_str(int opcode)
} }
} }
static int pdsc_devcmd_wait(struct pdsc *pdsc, int max_seconds) static int pdsc_devcmd_wait(struct pdsc *pdsc, u8 opcode, int max_seconds)
{ {
struct device *dev = pdsc->dev; struct device *dev = pdsc->dev;
unsigned long start_time; unsigned long start_time;
@ -131,9 +131,6 @@ static int pdsc_devcmd_wait(struct pdsc *pdsc, int max_seconds)
int done = 0; int done = 0;
int err = 0; int err = 0;
int status; int status;
int opcode;
opcode = ioread8(&pdsc->cmd_regs->cmd.opcode);
start_time = jiffies; start_time = jiffies;
max_wait = start_time + (max_seconds * HZ); max_wait = start_time + (max_seconds * HZ);
@ -180,10 +177,10 @@ int pdsc_devcmd_locked(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
memcpy_toio(&pdsc->cmd_regs->cmd, cmd, sizeof(*cmd)); memcpy_toio(&pdsc->cmd_regs->cmd, cmd, sizeof(*cmd));
pdsc_devcmd_dbell(pdsc); pdsc_devcmd_dbell(pdsc);
err = pdsc_devcmd_wait(pdsc, max_seconds); err = pdsc_devcmd_wait(pdsc, cmd->opcode, max_seconds);
memcpy_fromio(comp, &pdsc->cmd_regs->comp, sizeof(*comp)); memcpy_fromio(comp, &pdsc->cmd_regs->comp, sizeof(*comp));
if (err == -ENXIO || err == -ETIMEDOUT) if ((err == -ENXIO || err == -ETIMEDOUT) && pdsc->wq)
queue_work(pdsc->wq, &pdsc->health_work); queue_work(pdsc->wq, &pdsc->health_work);
return err; return err;

View file

@ -10,6 +10,9 @@ pdsc_viftype *pdsc_dl_find_viftype_by_id(struct pdsc *pdsc,
{ {
int vt; int vt;
if (!pdsc->viftype_status)
return NULL;
for (vt = 0; vt < PDS_DEV_TYPE_MAX; vt++) { for (vt = 0; vt < PDS_DEV_TYPE_MAX; vt++) {
if (pdsc->viftype_status[vt].dl_id == dl_id) if (pdsc->viftype_status[vt].dl_id == dl_id)
return &pdsc->viftype_status[vt]; return &pdsc->viftype_status[vt];

View file

@ -17794,10 +17794,7 @@ static int tg3_init_one(struct pci_dev *pdev,
tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
tnapi->int_mbox = intmbx; tnapi->int_mbox = intmbx;
if (i <= 4) intmbx += 0x8;
intmbx += 0x8;
else
intmbx += 0x4;
tnapi->consmbox = rcvmbx; tnapi->consmbox = rcvmbx;
tnapi->prodmbox = sndmbx; tnapi->prodmbox = sndmbx;

View file

@ -131,6 +131,8 @@ static void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
case READ_TIME: case READ_TIME:
cmd_val |= GLTSYN_CMD_READ_TIME; cmd_val |= GLTSYN_CMD_READ_TIME;
break; break;
case ICE_PTP_NOP:
break;
} }
wr32(hw, GLTSYN_CMD, cmd_val); wr32(hw, GLTSYN_CMD, cmd_val);
@ -1226,18 +1228,18 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
} }
/** /**
* ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command * ice_ptp_write_port_cmd_e822 - Prepare a single PHY port for a timer command
* @hw: pointer to HW struct * @hw: pointer to HW struct
* @port: Port to which cmd has to be sent * @port: Port to which cmd has to be sent
* @cmd: Command to be sent to the port * @cmd: Command to be sent to the port
* *
* Prepare the requested port for an upcoming timer sync command. * Prepare the requested port for an upcoming timer sync command.
* *
* Note there is no equivalent of this operation on E810, as that device * Do not use this function directly. If you want to configure exactly one
* always handles all external PHYs internally. * port, use ice_ptp_one_port_cmd() instead.
*/ */
static int static int
ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd) ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)
{ {
u32 cmd_val, val; u32 cmd_val, val;
u8 tmr_idx; u8 tmr_idx;
@ -1261,6 +1263,8 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)
case ADJ_TIME_AT_TIME: case ADJ_TIME_AT_TIME:
cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME; cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
break; break;
case ICE_PTP_NOP:
break;
} }
/* Tx case */ /* Tx case */
@ -1306,6 +1310,39 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)
return 0; return 0;
} }
/**
* ice_ptp_one_port_cmd - Prepare one port for a timer command
* @hw: pointer to the HW struct
* @configured_port: the port to configure with configured_cmd
* @configured_cmd: timer command to prepare on the configured_port
*
* Prepare the configured_port for the configured_cmd, and prepare all other
* ports for ICE_PTP_NOP. This causes the configured_port to execute the
* desired command while all other ports perform no operation.
*/
static int
ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
enum ice_ptp_tmr_cmd configured_cmd)
{
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
enum ice_ptp_tmr_cmd cmd;
int err;
if (port == configured_port)
cmd = configured_cmd;
else
cmd = ICE_PTP_NOP;
err = ice_ptp_write_port_cmd_e822(hw, port, cmd);
if (err)
return err;
}
return 0;
}
/** /**
* ice_ptp_port_cmd_e822 - Prepare all ports for a timer command * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command
* @hw: pointer to the HW struct * @hw: pointer to the HW struct
@ -1322,7 +1359,7 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
int err; int err;
err = ice_ptp_one_port_cmd(hw, port, cmd); err = ice_ptp_write_port_cmd_e822(hw, port, cmd);
if (err) if (err)
return err; return err;
} }
@ -2252,6 +2289,9 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
if (err) if (err)
goto err_unlock; goto err_unlock;
/* Do not perform any action on the main timer */
ice_ptp_src_cmd(hw, ICE_PTP_NOP);
/* Issue the sync to activate the time adjustment */ /* Issue the sync to activate the time adjustment */
ice_ptp_exec_tmr_cmd(hw); ice_ptp_exec_tmr_cmd(hw);
@ -2372,6 +2412,9 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
if (err) if (err)
return err; return err;
/* Do not perform any action on the main timer */
ice_ptp_src_cmd(hw, ICE_PTP_NOP);
ice_ptp_exec_tmr_cmd(hw); ice_ptp_exec_tmr_cmd(hw);
err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
@ -2847,6 +2890,8 @@ static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
case ADJ_TIME_AT_TIME: case ADJ_TIME_AT_TIME:
cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
break; break;
case ICE_PTP_NOP:
return 0;
} }
/* Read, modify, write */ /* Read, modify, write */

View file

@ -9,7 +9,8 @@ enum ice_ptp_tmr_cmd {
INIT_INCVAL, INIT_INCVAL,
ADJ_TIME, ADJ_TIME,
ADJ_TIME_AT_TIME, ADJ_TIME_AT_TIME,
READ_TIME READ_TIME,
ICE_PTP_NOP,
}; };
enum ice_ptp_serdes { enum ice_ptp_serdes {

View file

@ -4814,6 +4814,10 @@ void igb_configure_rx_ring(struct igb_adapter *adapter,
static void igb_set_rx_buffer_len(struct igb_adapter *adapter, static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
struct igb_ring *rx_ring) struct igb_ring *rx_ring)
{ {
#if (PAGE_SIZE < 8192)
struct e1000_hw *hw = &adapter->hw;
#endif
/* set build_skb and buffer size flags */ /* set build_skb and buffer size flags */
clear_ring_build_skb_enabled(rx_ring); clear_ring_build_skb_enabled(rx_ring);
clear_ring_uses_large_buffer(rx_ring); clear_ring_uses_large_buffer(rx_ring);
@ -4824,10 +4828,9 @@ static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
set_ring_build_skb_enabled(rx_ring); set_ring_build_skb_enabled(rx_ring);
#if (PAGE_SIZE < 8192) #if (PAGE_SIZE < 8192)
if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB ||
return; rd32(E1000_RCTL) & E1000_RCTL_SBP)
set_ring_uses_large_buffer(rx_ring);
set_ring_uses_large_buffer(rx_ring);
#endif #endif
} }

View file

@ -355,8 +355,8 @@ int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause,
void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable) void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable)
{ {
u64 cfg, pfc_class_mask_cfg;
rpm_t *rpm = rpmd; rpm_t *rpm = rpmd;
u64 cfg;
/* ALL pause frames received are completely ignored */ /* ALL pause frames received are completely ignored */
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
@ -380,9 +380,11 @@ void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable)
rpm_write(rpm, 0, RPMX_CMR_CHAN_MSK_OR, ~0ULL); rpm_write(rpm, 0, RPMX_CMR_CHAN_MSK_OR, ~0ULL);
/* Disable all PFC classes */ /* Disable all PFC classes */
cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL); pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
RPMX_CMRX_PRT_CBFC_CTL;
cfg = rpm_read(rpm, lmac_id, pfc_class_mask_cfg);
cfg = FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg); cfg = FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg);
rpm_write(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL, cfg); rpm_write(rpm, lmac_id, pfc_class_mask_cfg, cfg);
} }
int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat) int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat)
@ -605,8 +607,11 @@ int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 p
if (!is_lmac_valid(rpm, lmac_id)) if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV; return -ENODEV;
pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
RPMX_CMRX_PRT_CBFC_CTL;
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
class_en = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL); class_en = rpm_read(rpm, lmac_id, pfc_class_mask_cfg);
pfc_en |= FIELD_GET(RPM_PFC_CLASS_MASK, class_en); pfc_en |= FIELD_GET(RPM_PFC_CLASS_MASK, class_en);
if (rx_pause) { if (rx_pause) {
@ -635,10 +640,6 @@ int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 p
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE; cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
RPMX_CMRX_PRT_CBFC_CTL;
rpm_write(rpm, lmac_id, pfc_class_mask_cfg, class_en); rpm_write(rpm, lmac_id, pfc_class_mask_cfg, class_en);
return 0; return 0;

View file

@ -806,6 +806,7 @@ void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq)
mutex_unlock(&pfvf->mbox.lock); mutex_unlock(&pfvf->mbox.lock);
} }
EXPORT_SYMBOL(otx2_txschq_free_one);
void otx2_txschq_stop(struct otx2_nic *pfvf) void otx2_txschq_stop(struct otx2_nic *pfvf)
{ {
@ -1434,7 +1435,7 @@ int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
} }
pp_params.flags = PP_FLAG_PAGE_FRAG | PP_FLAG_DMA_MAP; pp_params.flags = PP_FLAG_PAGE_FRAG | PP_FLAG_DMA_MAP;
pp_params.pool_size = numptrs; pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs);
pp_params.nid = NUMA_NO_NODE; pp_params.nid = NUMA_NO_NODE;
pp_params.dev = pfvf->dev; pp_params.dev = pfvf->dev;
pp_params.dma_dir = DMA_FROM_DEVICE; pp_params.dma_dir = DMA_FROM_DEVICE;

View file

@ -70,7 +70,7 @@ static int otx2_pfc_txschq_alloc_one(struct otx2_nic *pfvf, u8 prio)
* link config level. These rest of the scheduler can be * link config level. These rest of the scheduler can be
* same as hw.txschq_list. * same as hw.txschq_list.
*/ */
for (lvl = 0; lvl < pfvf->hw.txschq_link_cfg_lvl; lvl++) for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++)
req->schq[lvl] = 1; req->schq[lvl] = 1;
rc = otx2_sync_mbox_msg(&pfvf->mbox); rc = otx2_sync_mbox_msg(&pfvf->mbox);
@ -83,7 +83,7 @@ static int otx2_pfc_txschq_alloc_one(struct otx2_nic *pfvf, u8 prio)
return PTR_ERR(rsp); return PTR_ERR(rsp);
/* Setup transmit scheduler list */ /* Setup transmit scheduler list */
for (lvl = 0; lvl < pfvf->hw.txschq_link_cfg_lvl; lvl++) { for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++) {
if (!rsp->schq[lvl]) if (!rsp->schq[lvl])
return -ENOSPC; return -ENOSPC;
@ -125,19 +125,12 @@ int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf)
static int otx2_pfc_txschq_stop_one(struct otx2_nic *pfvf, u8 prio) static int otx2_pfc_txschq_stop_one(struct otx2_nic *pfvf, u8 prio)
{ {
struct nix_txsch_free_req *free_req; int lvl;
mutex_lock(&pfvf->mbox.lock);
/* free PFC TLx nodes */ /* free PFC TLx nodes */
free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++)
if (!free_req) { otx2_txschq_free_one(pfvf, lvl,
mutex_unlock(&pfvf->mbox.lock); pfvf->pfc_schq_list[lvl][prio]);
return -ENOMEM;
}
free_req->flags = TXSCHQ_FREE_ALL;
otx2_sync_mbox_msg(&pfvf->mbox);
mutex_unlock(&pfvf->mbox.lock);
pfvf->pfc_alloc_status[prio] = false; pfvf->pfc_alloc_status[prio] = false;
return 0; return 0;

View file

@ -23,6 +23,8 @@
#define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN) #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
#define OTX2_MIN_MTU 60 #define OTX2_MIN_MTU 60
#define OTX2_PAGE_POOL_SZ 2048
#define OTX2_MAX_GSO_SEGS 255 #define OTX2_MAX_GSO_SEGS 255
#define OTX2_MAX_FRAGS_IN_SQE 9 #define OTX2_MAX_FRAGS_IN_SQE 9

View file

@ -32,16 +32,13 @@
#include <linux/clocksource.h> #include <linux/clocksource.h>
#include <linux/highmem.h> #include <linux/highmem.h>
#include <linux/log2.h>
#include <linux/ptp_clock_kernel.h> #include <linux/ptp_clock_kernel.h>
#include <rdma/mlx5-abi.h> #include <rdma/mlx5-abi.h>
#include "lib/eq.h" #include "lib/eq.h"
#include "en.h" #include "en.h"
#include "clock.h" #include "clock.h"
enum {
MLX5_CYCLES_SHIFT = 31
};
enum { enum {
MLX5_PIN_MODE_IN = 0x0, MLX5_PIN_MODE_IN = 0x0,
MLX5_PIN_MODE_OUT = 0x1, MLX5_PIN_MODE_OUT = 0x1,
@ -93,6 +90,31 @@ static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev)
return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify); return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify);
} }
static u32 mlx5_ptp_shift_constant(u32 dev_freq_khz)
{
/* Optimal shift constant leads to corrections above just 1 scaled ppm.
*
* Two sets of equations are needed to derive the optimal shift
* constant for the cyclecounter.
*
* dev_freq_khz * 1000 / 2^shift_constant = 1 scaled_ppm
* ppb = scaled_ppm * 1000 / 2^16
*
* Using the two equations together
*
* dev_freq_khz * 1000 / 1 scaled_ppm = 2^shift_constant
* dev_freq_khz * 2^16 / 1 ppb = 2^shift_constant
* dev_freq_khz = 2^(shift_constant - 16)
*
* then yields
*
* shift_constant = ilog2(dev_freq_khz) + 16
*/
return min(ilog2(dev_freq_khz) + 16,
ilog2((U32_MAX / NSEC_PER_MSEC) * dev_freq_khz));
}
static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp)
{ {
struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
@ -909,7 +931,7 @@ static void mlx5_timecounter_init(struct mlx5_core_dev *mdev)
dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz); dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz);
timer->cycles.read = read_internal_timer; timer->cycles.read = read_internal_timer;
timer->cycles.shift = MLX5_CYCLES_SHIFT; timer->cycles.shift = mlx5_ptp_shift_constant(dev_freq);
timer->cycles.mult = clocksource_khz2mult(dev_freq, timer->cycles.mult = clocksource_khz2mult(dev_freq,
timer->cycles.shift); timer->cycles.shift);
timer->nominal_c_mult = timer->cycles.mult; timer->nominal_c_mult = timer->cycles.mult;

View file

@ -405,7 +405,8 @@ mlxsw_hwmon_module_temp_label_show(struct device *dev,
container_of(attr, struct mlxsw_hwmon_attr, dev_attr); container_of(attr, struct mlxsw_hwmon_attr, dev_attr);
return sprintf(buf, "front panel %03u\n", return sprintf(buf, "front panel %03u\n",
mlxsw_hwmon_attr->type_index); mlxsw_hwmon_attr->type_index + 1 -
mlxsw_hwmon_attr->mlxsw_hwmon_dev->sensor_count);
} }
static ssize_t static ssize_t

View file

@ -48,6 +48,7 @@
#define MLXSW_I2C_MBOX_SIZE_BITS 12 #define MLXSW_I2C_MBOX_SIZE_BITS 12
#define MLXSW_I2C_ADDR_BUF_SIZE 4 #define MLXSW_I2C_ADDR_BUF_SIZE 4
#define MLXSW_I2C_BLK_DEF 32 #define MLXSW_I2C_BLK_DEF 32
#define MLXSW_I2C_BLK_MAX 100
#define MLXSW_I2C_RETRY 5 #define MLXSW_I2C_RETRY 5
#define MLXSW_I2C_TIMEOUT_MSECS 5000 #define MLXSW_I2C_TIMEOUT_MSECS 5000
#define MLXSW_I2C_MAX_DATA_SIZE 256 #define MLXSW_I2C_MAX_DATA_SIZE 256
@ -444,7 +445,7 @@ mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size,
} else { } else {
/* No input mailbox is case of initialization query command. */ /* No input mailbox is case of initialization query command. */
reg_size = MLXSW_I2C_MAX_DATA_SIZE; reg_size = MLXSW_I2C_MAX_DATA_SIZE;
num = reg_size / mlxsw_i2c->block_size; num = DIV_ROUND_UP(reg_size, mlxsw_i2c->block_size);
if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) { if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
dev_err(&client->dev, "Could not acquire lock"); dev_err(&client->dev, "Could not acquire lock");
@ -653,7 +654,7 @@ static int mlxsw_i2c_probe(struct i2c_client *client)
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
mlxsw_i2c->block_size = max_t(u16, MLXSW_I2C_BLK_DEF, mlxsw_i2c->block_size = min_t(u16, MLXSW_I2C_BLK_MAX,
min_t(u16, quirks->max_read_len, min_t(u16, quirks->max_read_len,
quirks->max_write_len)); quirks->max_write_len));
} else { } else {

View file

@ -5239,13 +5239,9 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
/* Disable ASPM L1 as that cause random device stop working /* Disable ASPM L1 as that cause random device stop working
* problems as well as full system hangs for some PCIe devices users. * problems as well as full system hangs for some PCIe devices users.
* Chips from RTL8168h partially have issues with L1.2, but seem
* to work fine with L1 and L1.1.
*/ */
if (rtl_aspm_is_safe(tp)) if (rtl_aspm_is_safe(tp))
rc = 0; rc = 0;
else if (tp->mac_version >= RTL_GIGA_MAC_VER_46)
rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2);
else else
rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
tp->aspm_manageable = !rc; tp->aspm_manageable = !rc;

View file

@ -1359,7 +1359,9 @@ static int efx_ptp_insert_multicast_filters(struct efx_nic *efx)
goto fail; goto fail;
rc = efx_ptp_insert_eth_multicast_filter(efx); rc = efx_ptp_insert_eth_multicast_filter(efx);
if (rc < 0)
/* Not all firmware variants support this filter */
if (rc < 0 && rc != -EPROTONOSUPPORT)
goto fail; goto fail;
} }

View file

@ -53,6 +53,10 @@ static inline bool dev_is_mac_header_xmit(const struct net_device *dev)
case ARPHRD_NONE: case ARPHRD_NONE:
case ARPHRD_RAWIP: case ARPHRD_RAWIP:
case ARPHRD_PIMREG: case ARPHRD_PIMREG:
/* PPP adds its l2 header automatically in ppp_start_xmit().
* This makes it look like an l3 device to __bpf_redirect() and tcf_mirred_init().
*/
case ARPHRD_PPP:
return false; return false;
default: default:
return true; return true;

View file

@ -254,12 +254,17 @@ static int dccp_v4_err(struct sk_buff *skb, u32 info)
int err; int err;
struct net *net = dev_net(skb->dev); struct net *net = dev_net(skb->dev);
/* Only need dccph_dport & dccph_sport which are the first /* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x,
* 4 bytes in dccp header. * which is in byte 7 of the dccp header.
* Our caller (icmp_socket_deliver()) already pulled 8 bytes for us. * Our caller (icmp_socket_deliver()) already pulled 8 bytes for us.
*
* Later on, we want to access the sequence number fields, which are
* beyond 8 bytes, so we have to pskb_may_pull() ourselves.
*/ */
BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_sport) > 8); dh = (struct dccp_hdr *)(skb->data + offset);
BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_dport) > 8); if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh)))
return -EINVAL;
iph = (struct iphdr *)skb->data;
dh = (struct dccp_hdr *)(skb->data + offset); dh = (struct dccp_hdr *)(skb->data + offset);
sk = __inet_lookup_established(net, &dccp_hashinfo, sk = __inet_lookup_established(net, &dccp_hashinfo,

View file

@ -74,7 +74,7 @@ static inline __u64 dccp_v6_init_sequence(struct sk_buff *skb)
static int dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, static int dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt,
u8 type, u8 code, int offset, __be32 info) u8 type, u8 code, int offset, __be32 info)
{ {
const struct ipv6hdr *hdr = (const struct ipv6hdr *)skb->data; const struct ipv6hdr *hdr;
const struct dccp_hdr *dh; const struct dccp_hdr *dh;
struct dccp_sock *dp; struct dccp_sock *dp;
struct ipv6_pinfo *np; struct ipv6_pinfo *np;
@ -83,12 +83,17 @@ static int dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt,
__u64 seq; __u64 seq;
struct net *net = dev_net(skb->dev); struct net *net = dev_net(skb->dev);
/* Only need dccph_dport & dccph_sport which are the first /* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x,
* 4 bytes in dccp header. * which is in byte 7 of the dccp header.
* Our caller (icmpv6_notify()) already pulled 8 bytes for us. * Our caller (icmpv6_notify()) already pulled 8 bytes for us.
*
* Later on, we want to access the sequence number fields, which are
* beyond 8 bytes, so we have to pskb_may_pull() ourselves.
*/ */
BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_sport) > 8); dh = (struct dccp_hdr *)(skb->data + offset);
BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_dport) > 8); if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh)))
return -EINVAL;
hdr = (const struct ipv6hdr *)skb->data;
dh = (struct dccp_hdr *)(skb->data + offset); dh = (struct dccp_hdr *)(skb->data + offset);
sk = __inet6_lookup_established(net, &dccp_hashinfo, sk = __inet6_lookup_established(net, &dccp_hashinfo,

View file

@ -660,6 +660,11 @@ static int nr_connect(struct socket *sock, struct sockaddr *uaddr,
goto out_release; goto out_release;
} }
if (sock->state == SS_CONNECTING) {
err = -EALREADY;
goto out_release;
}
sk->sk_state = TCP_CLOSE; sk->sk_state = TCP_CLOSE;
sock->state = SS_UNCONNECTED; sock->state = SS_UNCONNECTED;

View file

@ -1011,6 +1011,10 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
if (parent == NULL) if (parent == NULL)
return -ENOENT; return -ENOENT;
} }
if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) {
NL_SET_ERR_MSG(extack, "Invalid parent - parent class must have FSC");
return -EINVAL;
}
if (classid == 0 || TC_H_MAJ(classid ^ sch->handle) != 0) if (classid == 0 || TC_H_MAJ(classid ^ sch->handle) != 0)
return -EINVAL; return -EINVAL;