mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-01-22 07:53:11 -05:00
4c551165e7
- Consolidation of the machine_kexec_mask_interrupts() by providing a
generic implementation and replacing the copy & pasta orgy in the
relevant architectures.
- Prevent unconditional operations on interrupt chips during kexec
shutdown, which can trigger warnings in certain cases when the
underlying interrupt has been shut down before.
- Make the enforcement of interrupt handling in interrupt context
unconditionally available, so that it actually works for non x86
related interrupt chips. The earlier enablement for ARM GIC chips set
the required chip flag, but did not notice that the check was hidden
behind a config switch which is not selected by ARM[64].
- Decrapify the handling of deferred interrupt affinity setting. Some
interrupt chips require that affinity changes are made from the context
of handling an interrupt to avoid certain race conditions. For x86 this
was the default, but with interrupt remapping this requirement was
lifted and a flag was introduced which tells the core code that
affinity changes can be done in any context. Unrestricted affinity
changes are the default for the majority of interrupt chips. RISCV has
the requirement to add the deferred mode to one of it's interrupt
controllers, but with the original implementation this would require to
add the any context flag to all other RISC-V interrupt chips. That's
backwards, so reverse the logic and require that chips, which need the
deferred mode have to be marked accordingly. That avoids chasing the
'sane' chips and marking them.
- Add multi-node support to the Loongarch AVEC interrupt controller
driver.
- The usual tiny cleanups, fixes and improvements all over the place.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmePkVITHHRnbHhAbGlu
dXRyb25peC5kZQAKCRCmGPVMDXSYoRbQD/9bHVph/V9Ekl7JAX3aY4gG4JbRhOc7
dp1VAcHRhktRfoTztYRbjsbMu2nvZ58GKA8bkOS2jHSF/m3PbkIJfOhwk0YdIAoa
+kdy5yDgqCGfkqW43DN4Cr+CnzGjWMitw67tFp3fhwehMDpDjdt2L28IjtanSS0f
hO6FV7o65MWeJwxk4Isb2/nvkO+X23Lrp6RrWS8SXBnF9FFXxiPIg/fiOPTizhCh
1W/bSGxLLb9WwsVzmlGAKVFlXDij0QGaIUug2fdVZ63OsELXD7tJrLSPG133yk92
ppIa0s6BT4IBsfM00us4hG15PkLuJmP3yWWcoquG0rP8Wq58VOXiN6+rcJIyvB+5
mWceTH6IKfZGoRQKwXC7BxeBAIb147reiJtb06meq1/8ADIvzafiNy0c8x9i/UaV
QiyhPVENjaGCGDomZmJQqN7Yb02Wge1k8InQnodDrHxZNl/bX/B1Z8Bxd0n6hPHg
NSJXYif2AxgaddpohsdygqRDbT6SNyQdj7YjJFY5qAGJ3yFyJ4JB6WTqkWW4o1vH
3FVqdAnJmejAmmYSkah0Hkem2T5QASQmTWb93PLxiV6q+d0NM8stWAujjyVdIV/B
W4Uj9mQ20cz54TjLtxqX+A1k6KcqOWRgh1l2QbUlFsgsOP3V8yz47yqYdR9qMWlO
9kNEjI3sw+G/IQ==
=q4rj
-----END PGP SIGNATURE-----
Merge tag 'irq-core-2025-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull interrupt subsystem updates from Thomas Gleixner:
- Consolidate the machine_kexec_mask_interrupts() by providing a
generic implementation and replacing the copy & pasta orgy in the
relevant architectures.
- Prevent unconditional operations on interrupt chips during kexec
shutdown, which can trigger warnings in certain cases when the
underlying interrupt has been shut down before.
- Make the enforcement of interrupt handling in interrupt context
unconditionally available, so that it actually works for non x86
related interrupt chips. The earlier enablement for ARM GIC chips set
the required chip flag, but did not notice that the check was hidden
behind a config switch which is not selected by ARM[64].
- Decrapify the handling of deferred interrupt affinity setting.
Some interrupt chips require that affinity changes are made from the
context of handling an interrupt to avoid certain race conditions.
For x86 this was the default, but with interrupt remapping this
requirement was lifted and a flag was introduced which tells the core
code that affinity changes can be done in any context. Unrestricted
affinity changes are the default for the majority of interrupt chips.
RISCV has the requirement to add the deferred mode to one of it's
interrupt controllers, but with the original implementation this
would require to add the any context flag to all other RISC-V
interrupt chips. That's backwards, so reverse the logic and require
that chips, which need the deferred mode have to be marked
accordingly. That avoids chasing the 'sane' chips and marking them.
- Add multi-node support to the Loongarch AVEC interrupt controller
driver.
- The usual tiny cleanups, fixes and improvements all over the place.
* tag 'irq-core-2025-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
genirq/generic_chip: Export irq_gc_mask_disable_and_ack_set()
genirq/timings: Add kernel-doc for a function parameter
genirq: Remove IRQ_MOVE_PCNTXT and related code
x86/apic: Convert to IRQCHIP_MOVE_DEFERRED
genirq: Provide IRQCHIP_MOVE_DEFERRED
hexagon: Remove GENERIC_PENDING_IRQ leftover
ARC: Remove GENERIC_PENDING_IRQ
genirq: Remove handle_enforce_irqctx() wrapper
genirq: Make handle_enforce_irqctx() unconditionally available
irqchip/loongarch-avec: Add multi-nodes topology support
irqchip/ts4800: Replace seq_printf() by seq_puts()
irqchip/ti-sci-inta : Add module build support
irqchip/ti-sci-intr: Add module build support
irqchip/irq-brcmstb-l2: Replace brcmstb_l2_mask_and_ack() by generic function
irqchip: keystone: Use syscon_regmap_lookup_by_phandle_args
genirq/kexec: Prevent redundant IRQ masking by checking state before shutdown
kexec: Consolidate machine_kexec_mask_interrupts() implementation
genirq: Reuse irq_thread_fn() for forced thread case
genirq: Move irq_thread_fn() further up in the code
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|---|---|---|
| .. | ||
| alphascale_asm9260-icoll.h | ||
| exynos-combiner.c | ||
| irq-al-fic.c | ||
| irq-alpine-msi.c | ||
| irq-apple-aic.c | ||
| irq-armada-370-xp.c | ||
| irq-aspeed-i2c-ic.c | ||
| irq-aspeed-intc.c | ||
| irq-aspeed-scu-ic.c | ||
| irq-aspeed-vic.c | ||
| irq-ath79-cpu.c | ||
| irq-ath79-misc.c | ||
| irq-atmel-aic-common.c | ||
| irq-atmel-aic-common.h | ||
| irq-atmel-aic.c | ||
| irq-atmel-aic5.c | ||
| irq-bcm2835.c | ||
| irq-bcm2836.c | ||
| irq-bcm6345-l1.c | ||
| irq-bcm7038-l1.c | ||
| irq-bcm7120-l2.c | ||
| irq-brcmstb-l2.c | ||
| irq-clps711x.c | ||
| irq-crossbar.c | ||
| irq-csky-apb-intc.c | ||
| irq-csky-mpintc.c | ||
| irq-davinci-cp-intc.c | ||
| irq-digicolor.c | ||
| irq-dw-apb-ictl.c | ||
| irq-ftintc010.c | ||
| irq-gic-common.c | ||
| irq-gic-common.h | ||
| irq-gic-pm.c | ||
| irq-gic-realview.c | ||
| irq-gic-v2m.c | ||
| irq-gic-v3-its-fsl-mc-msi.c | ||
| irq-gic-v3-its-msi-parent.c | ||
| irq-gic-v3-its.c | ||
| irq-gic-v3-mbi.c | ||
| irq-gic-v3.c | ||
| irq-gic-v4.c | ||
| irq-gic.c | ||
| irq-goldfish-pic.c | ||
| irq-hip04.c | ||
| irq-i8259.c | ||
| irq-idt3243x.c | ||
| irq-imgpdc.c | ||
| irq-imx-gpcv2.c | ||
| irq-imx-intmux.c | ||
| irq-imx-irqsteer.c | ||
| irq-imx-mu-msi.c | ||
| irq-ingenic-tcu.c | ||
| irq-ingenic.c | ||
| irq-ixp4xx.c | ||
| irq-jcore-aic.c | ||
| irq-keystone.c | ||
| irq-lan966x-oic.c | ||
| irq-loongarch-avec.c | ||
| irq-loongarch-cpu.c | ||
| irq-loongson-eiointc.c | ||
| irq-loongson-htpic.c | ||
| irq-loongson-htvec.c | ||
| irq-loongson-liointc.c | ||
| irq-loongson-pch-lpc.c | ||
| irq-loongson-pch-msi.c | ||
| irq-loongson-pch-pic.c | ||
| irq-loongson.h | ||
| irq-lpc32xx.c | ||
| irq-ls-extirq.c | ||
| irq-ls-scfg-msi.c | ||
| irq-ls1x.c | ||
| irq-madera.c | ||
| irq-mbigen.c | ||
| irq-mchp-eic.c | ||
| irq-meson-gpio.c | ||
| irq-mips-cpu.c | ||
| irq-mips-gic.c | ||
| irq-mmp.c | ||
| irq-mscc-ocelot.c | ||
| irq-msi-lib.c | ||
| irq-msi-lib.h | ||
| irq-mst-intc.c | ||
| irq-mtk-cirq.c | ||
| irq-mtk-sysirq.c | ||
| irq-mvebu-gicp.c | ||
| irq-mvebu-icu.c | ||
| irq-mvebu-odmi.c | ||
| irq-mvebu-pic.c | ||
| irq-mvebu-sei.c | ||
| irq-mxs.c | ||
| irq-nvic.c | ||
| irq-omap-intc.c | ||
| irq-ompic.c | ||
| irq-or1k-pic.c | ||
| irq-orion.c | ||
| irq-owl-sirq.c | ||
| irq-partition-percpu.c | ||
| irq-pic32-evic.c | ||
| irq-pruss-intc.c | ||
| irq-qcom-mpm.c | ||
| irq-rda-intc.c | ||
| irq-realtek-rtl.c | ||
| irq-renesas-intc-irqpin.c | ||
| irq-renesas-irqc.c | ||
| irq-renesas-rza1.c | ||
| irq-renesas-rzg2l.c | ||
| irq-renesas-rzv2h.c | ||
| irq-riscv-aplic-direct.c | ||
| irq-riscv-aplic-main.c | ||
| irq-riscv-aplic-main.h | ||
| irq-riscv-aplic-msi.c | ||
| irq-riscv-imsic-early.c | ||
| irq-riscv-imsic-platform.c | ||
| irq-riscv-imsic-state.c | ||
| irq-riscv-imsic-state.h | ||
| irq-riscv-intc.c | ||
| irq-sa11x0.c | ||
| irq-sifive-plic.c | ||
| irq-sl28cpld.c | ||
| irq-sni-exiu.c | ||
| irq-sp7021-intc.c | ||
| irq-st.c | ||
| irq-starfive-jh8100-intc.c | ||
| irq-stm32-exti.c | ||
| irq-stm32mp-exti.c | ||
| irq-sun4i.c | ||
| irq-sun6i-r.c | ||
| irq-sunxi-nmi.c | ||
| irq-tb10x.c | ||
| irq-tegra.c | ||
| irq-thead-c900-aclint-sswi.c | ||
| irq-ti-sci-inta.c | ||
| irq-ti-sci-intr.c | ||
| irq-ts4800.c | ||
| irq-uniphier-aidet.c | ||
| irq-versatile-fpga.c | ||
| irq-vf610-mscm-ir.c | ||
| irq-vic.c | ||
| irq-vt8500.c | ||
| irq-wpcm450-aic.c | ||
| irq-xilinx-intc.c | ||
| irq-xtensa-mx.c | ||
| irq-xtensa-pic.c | ||
| irq-zevio.c | ||
| irqchip.c | ||
| Kconfig | ||
| Makefile | ||
| qcom-irq-combiner.c | ||
| qcom-pdc.c | ||
| spear-shirq.c | ||