Fabrice Gasnier fd5ac974fc counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update ... The ARR (auto reload register) and CMP (compare) registers are successively written. The status bits to check the update of these registers are polled together with regmap_read_poll_timeout(). The condition to end the loop may become true, even if one of the register isn't correctly updated. So ensure both status bits are set before clearing them. Fixes: d8958824cf ("iio: counter: Add support for STM32 LPTimer") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20221123133609.465614-1-fabrice.gasnier@foss.st.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>		2022-11-26 16:49:28 -05:00
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104-quad-8.c	counter: 104-quad-8: Fix race getting function mode and direction	2022-10-23 20:39:26 -04:00
counter-chrdev.c
counter-chrdev.h
counter-core.c
counter-sysfs.c
counter-sysfs.h
ftm-quaddec.c
intel-qep.c
interrupt-cnt.c
Kconfig
Makefile
microchip-tcb-capture.c	counter: microchip-tcb-capture: Handle Signal1 read and Synapse	2022-10-23 20:38:49 -04:00
stm32-lptimer-cnt.c	counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update	2022-11-26 16:49:28 -05:00
stm32-timer-cnt.c
ti-ecap-capture.c	counter: ti-ecap-capture: fix IS_ERR() vs NULL check	2022-10-17 09:51:29 -04:00
ti-eqep.c