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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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93d46d465f
The default PLL2/3/4/6 multiplier and divider configurations are no longer used after the conversion to fixed or variable fractional PLL clock types. Note that the default configurations are still documented in the comments above the individual rcar_gen4_cpg_pll_config instances. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/d13526a86066992d6afdf9bee7c1a18da72f914f.1721648548.git.geert+renesas@glider.be
238 lines
8.3 KiB
C
238 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*
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* Based on r8a779a0-cpg-mssr.c
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen4-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A779F0_CLK_R,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL3,
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CLK_PLL5,
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CLK_PLL6,
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CLK_PLL1_DIV2,
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CLK_PLL2_DIV2,
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CLK_PLL3_DIV2,
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CLK_PLL5_DIV2,
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CLK_PLL5_DIV4,
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CLK_PLL6_DIV2,
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CLK_S0,
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CLK_SASYNCPER,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_OCO,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
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DEF_GEN4_PLL_F9_24(".pll1", 1, CLK_PLL1, CLK_MAIN),
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DEF_GEN4_PLL_V9_24(".pll2", 2, CLK_PLL2, CLK_MAIN),
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DEF_GEN4_PLL_V9_24(".pll3", 3, CLK_PLL3, CLK_MAIN),
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DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
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DEF_GEN4_PLL_V9_24(".pll6", 6, CLK_PLL6, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
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DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
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DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
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DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
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DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
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DEF_RATE(".oco", CLK_OCO, 32768),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
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/* Core Clock Outputs */
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DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
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DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8),
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DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
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DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1),
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DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1),
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DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1),
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DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1),
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DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1),
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DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1),
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DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1),
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DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1),
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DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1),
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DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1),
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DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1),
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DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1),
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DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1),
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DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1),
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DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1),
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DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1),
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DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1),
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DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1),
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DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1),
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DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1),
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DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1),
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DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1),
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DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1),
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DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1),
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DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5_DIV2, 5, 1),
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DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
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DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
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DEF_FIXED("sasyncrt", R8A779F0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
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DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
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DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
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DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
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DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
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DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, CPG_SD0CKCR),
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DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
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DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),
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DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),
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DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
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};
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static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
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DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
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DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
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DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),
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DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1),
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DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
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DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
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DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
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DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
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DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
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DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
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DEF_MOD("msiof0", 618, R8A779F0_CLK_MSO),
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DEF_MOD("msiof1", 619, R8A779F0_CLK_MSO),
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DEF_MOD("msiof2", 620, R8A779F0_CLK_MSO),
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DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO),
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DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
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DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
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DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4),
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DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4),
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DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4),
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DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4),
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DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0),
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DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
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DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
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DEF_MOD("tmu0", 713, R8A779F0_CLK_SASYNCRT),
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DEF_MOD("tmu1", 714, R8A779F0_CLK_SASYNCPERD2),
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DEF_MOD("tmu2", 715, R8A779F0_CLK_SASYNCPERD2),
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DEF_MOD("tmu3", 716, R8A779F0_CLK_SASYNCPERD2),
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DEF_MOD("tmu4", 717, R8A779F0_CLK_SASYNCPERD2),
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DEF_MOD("wdt", 907, R8A779F0_CLK_R),
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DEF_MOD("cmt0", 910, R8A779F0_CLK_R),
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DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
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DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
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DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
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DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX),
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DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
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DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
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DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
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DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),
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};
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static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
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MOD_CLK_ID(907), /* WDT */
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};
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/*
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
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* 14 13 (MHz)
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* ------------------------------------------------------------------------
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* 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15
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* 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19
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* 1 0 Prohibited setting
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* 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
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(((md) & BIT(13)) >> 13))
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static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
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/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
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{ 1, 200, 1, 200, 1, 15, },
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{ 1, 160, 1, 160, 1, 19, },
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{ 0, 0, 0, 0, 0, 0, },
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{ 2, 160, 1, 160, 1, 38, },
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};
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static int __init r8a779f0_cpg_mssr_init(struct device *dev)
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{
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const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
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u32 cpg_mode;
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int error;
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error = rcar_rst_read_mode_pins(&cpg_mode);
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if (error)
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return error;
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cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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if (!cpg_pll_config->extal_div) {
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dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
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return -EINVAL;
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}
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return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
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}
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const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = {
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/* Core Clocks */
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.core_clks = r8a779f0_core_clks,
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.num_core_clks = ARRAY_SIZE(r8a779f0_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r8a779f0_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks),
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.num_hw_mod_clks = 28 * 32,
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/* Critical Module Clocks */
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.crit_mod_clks = r8a779f0_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks),
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/* Callbacks */
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.init = r8a779f0_cpg_mssr_init,
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.cpg_clk_register = rcar_gen4_cpg_clk_register,
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.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
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};
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