Samuel Holland 16d3b1af09 perf: RISC-V: Check standard event availability ... The RISC-V SBI PMU specification defines several standard hardware and cache events. Currently, all of these events are exposed to userspace, even when not actually implemented. They appear in the `perf list` output, and commands like `perf stat` try to use them. This is more than just a cosmetic issue, because the PMU driver's .add function fails for these events, which causes pmu_groups_sched_in() to prematurely stop scheduling in other (possibly valid) hardware events. Add logic to check which events are supported by the hardware (i.e. can be mapped to some counter), so only usable events are reported to userspace. Since the kernel does not know the mapping between events and possible counters, this check must happen during boot, when no counters are in use. Make the check asynchronous to minimize impact on boot time. Fixes: e999143459 ("RISC-V: Add perf platform driver based on SBI PMU extension") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20240628-misc_perf_fixes-v4-3-e01cfddcf035@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-07-03 12:56:22 -07:00
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amlogic
arm_cspmu
hisilicon
alibaba_uncore_drw_pmu.c
apple_m1_cpu_pmu.c
arm-cci.c
arm-ccn.c
arm-cmn.c
arm_dmc620_pmu.c
arm_dsu_pmu.c
arm_pmu.c
arm_pmu_acpi.c
arm_pmu_platform.c
arm_pmuv3.c
arm_smmuv3_pmu.c
arm_spe_pmu.c
cxl_pmu.c
dwc_pcie_pmu.c
fsl_imx8_ddr_perf.c
fsl_imx9_ddr_perf.c
Kconfig
Makefile
marvell_cn10k_ddr_pmu.c
marvell_cn10k_tad_pmu.c
qcom_l2_pmu.c
qcom_l3_pmu.c
riscv_pmu.c	drivers/perf: riscv: Do not update the event data if uptodate	2024-07-03 12:56:15 -07:00
riscv_pmu_legacy.c
riscv_pmu_sbi.c	perf: RISC-V: Check standard event availability	2024-07-03 12:56:22 -07:00
starfive_starlink_pmu.c
thunderx2_pmu.c
xgene_pmu.c