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f9786f419d
cpsw_cpts_rft_clk has got the choice of 3 clocksources -dpll_core_m4_ck -dpll_core_m5_ck -dpll_disp_m2_ck By default dpll_core_m4_ck is selected, witn this as clock source the CPTS doesnot work properly. It gives clockcheck errors while running PTP. clockcheck: clock jumped backward or running slower than expected! By selecting dpll_core_m5_ck as the clocksource fixes this issue. In AM335x dpll_core_m5_ck is the default clocksource. Signed-off-by: George Cherian <george.cherian@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| at91 | ||
| bcm | ||
| hisilicon | ||
| keystone | ||
| mmp | ||
| mvebu | ||
| mxs | ||
| qcom | ||
| rockchip | ||
| samsung | ||
| shmobile | ||
| sirf | ||
| socfpga | ||
| spear | ||
| st | ||
| sunxi | ||
| tegra | ||
| ti | ||
| ux500 | ||
| versatile | ||
| x86 | ||
| zynq | ||
| clk-axi-clkgen.c | ||
| clk-bcm2835.c | ||
| clk-composite.c | ||
| clk-devres.c | ||
| clk-divider.c | ||
| clk-efm32gg.c | ||
| clk-fixed-factor.c | ||
| clk-fixed-rate.c | ||
| clk-gate.c | ||
| clk-highbank.c | ||
| clk-ls1x.c | ||
| clk-max77686.c | ||
| clk-moxart.c | ||
| clk-mux.c | ||
| clk-nomadik.c | ||
| clk-nspire.c | ||
| clk-ppc-corenet.c | ||
| clk-s2mps11.c | ||
| clk-si570.c | ||
| clk-si5351.c | ||
| clk-si5351.h | ||
| clk-twl6040.c | ||
| clk-u300.c | ||
| clk-vt8500.c | ||
| clk-wm831x.c | ||
| clk-xgene.c | ||
| clk.c | ||
| clk.h | ||
| clkdev.c | ||
| Kconfig | ||
| Makefile | ||