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Kernel: Enable data and instruction cache on aarch64

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Enabling these will fix the Unsupported Exclusive or Atomic access data
fault we get on bare metal Raspberry Pi 3. On A53/A57 chips (and newer),
atomic compare-exchange operations require the data cache to be enabled.
This commit is contained in:
Andrew Kaster 2023-05-15 01:42:26 -06:00 • committed by Andrew Kaster
parent f62c646c28
commit 28d2e26678
1 changed files with 3 additions and 1 deletions
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4
Kernel/Arch/aarch64/MMU.cpp
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@ -214,8 +214,10 @@ static void activate_mmu()
Aarch64::TCR_EL1::write(tcr_el1);
// Enable MMU in the system control register
Aarch64::SCTLR_EL1 sctlr_el1 = Aarch64::SCTLR_EL1::read();
Aarch64::SCTLR_EL1 sctlr_el1 = Aarch64::SCTLR_EL1::reset_value();
sctlr_el1.M = 1; // Enable MMU
sctlr_el1.C = 1; // Enable data cache
sctlr_el1.I = 1; // Enable instruction cache
Aarch64::SCTLR_EL1::write(sctlr_el1);
Aarch64::Asm::flush();