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https://github.com/SerenityOS/serenity.git
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Kernel: Switch processor to EL1 immediately after boot on Aarch64
This commit is contained in:
Marcin Undak
Linus Groh
parent
d6021300d5
commit
2d9fa8146c
4 changed files with 321 additions and 16 deletions
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@ -22,3 +22,19 @@ Lstart:
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subs x0, x0, #1
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bne Lstart
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ret
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.global return_from_el3
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.type return_from_el3, @function
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return_from_el3:
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adr x0, start_in_el1
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msr elr_el3, x0
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eret
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start_in_el1:
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// Let stack start before .text for now.
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// 512 kiB (0x80000) of stack are probably not sufficient, especially once we give the other cores some stack too,
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// but for now it's ok.
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ldr x14, =start
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mov sp, x14
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b os_start
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@ -6,5 +6,10 @@
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#pragma once
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#include "AarchRegisters.h"
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extern "C" uint8_t get_current_exception_level();
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extern "C" void wait_cycles(int n);
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// CPU initialization functions
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extern "C" [[noreturn]] void return_from_el3();
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181
Kernel/Prekernel/Arch/aarch64/AarchRegisters.h
Normal file
181
Kernel/Prekernel/Arch/aarch64/AarchRegisters.h
Normal file
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@ -0,0 +1,181 @@
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/*
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* Copyright (c) 2021, Marcin Undak <mcinek@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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namespace Kernel {
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struct Aarch64_SCTLR_EL1 {
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int M : 1;
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int A : 1;
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int C : 1;
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int SA : 1;
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int SA0 : 1;
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int CP15BEN : 1;
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int _reserved6 : 1 = 0;
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int ITD : 1;
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int SED : 1;
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int UMA : 1;
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int _reserved10 : 1 = 0;
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int _reserved11 : 1 = 1;
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int I : 1;
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int EnDB : 1;
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int DZE : 1;
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int UCT : 1;
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int nTWI : 1;
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int _reserved17 : 1 = 0;
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int nTWE : 1;
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int WXN : 1;
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int _reserved20 : 1 = 1;
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int IESB : 1;
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int _reserved22 : 1 = 1;
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int SPAN : 1;
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int E0E : 1;
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int EE : 1;
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int UCI : 1;
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int EnDA : 1;
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int nTLSMD : 1;
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int LSMAOE : 1;
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int EnIB : 1;
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int EnIA : 1;
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int _reserved32 : 3 = 0;
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int BT0 : 1;
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int BT1 : 1;
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int ITFSB : 1;
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int TCF0 : 2;
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int TCF : 2;
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int ATA0 : 1;
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int ATA : 1;
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int DSSBS : 1;
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int TWEDEn : 1;
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int TWEDEL : 4;
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int _reserved50 : 4 = 0;
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int EnASR : 1;
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int EnAS0 : 1;
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int EnALS : 1;
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int EPAN : 1;
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int _reserved58 : 6 = 0;
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};
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static_assert(sizeof(Aarch64_SCTLR_EL1) == 8);
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struct Aarch64_HCR_EL2 {
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int VM : 1;
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int SWIO : 1;
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int PTW : 1;
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int FMO : 1;
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int IMO : 1;
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int AMO : 1;
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int VF : 1;
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int VI : 1;
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int VSE : 1;
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int FB : 1;
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int BSU : 2;
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int DC : 1;
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int TWI : 1;
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int TWE : 1;
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int TID0 : 1;
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int TID1 : 1;
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int TID2 : 1;
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int TID3 : 1;
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int TSC : 1;
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int TIPDCP : 1;
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int TACR : 1;
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int TSW : 1;
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int TPCF : 1;
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int TPU : 1;
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int TTLB : 1;
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int TVM : 1;
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int TGE : 1;
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int TDZ : 1;
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int HCD : 1;
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int TRVM : 1;
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int RW : 1;
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int CD : 1;
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int ID : 1;
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int E2H : 1;
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int TLOR : 1;
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int TERR : 1;
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int MIOCNCE : 1;
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int _reserved39 : 1 = 0;
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int APK : 1 = 0;
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int API : 1 = 0;
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int NV : 1 = 0;
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int NV1 : 1 = 0;
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int AT : 1 = 0;
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int _reserved45 : 18 = 0;
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};
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static_assert(sizeof(Aarch64_HCR_EL2) == 8);
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struct Aarch64_SCR_EL3 {
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int NS : 1;
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int IRQ : 1;
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int FIQ : 1;
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int EA : 1;
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int _reserved4 : 1 = 1;
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int _reserved5 : 1 = 1;
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int _reserved6 : 1 = 0;
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int SMD : 1;
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int HCE : 1;
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int SIF : 1;
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int RW : 1;
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int ST : 1;
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int TWI : 1;
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int TWE : 1;
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int TLOR : 1;
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int TERR : 1;
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int APK : 1;
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int API : 1;
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int EEL2 : 1;
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int EASE : 1;
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int NMEA : 1;
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int FIEN : 1;
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int _reserved22 : 3 = 0;
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int EnSCXT : 1;
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int ATA : 1;
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int FGTEn : 1;
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int ECVEn : 1;
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int TWEDEn : 1;
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int TWEDEL : 4;
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int _reserved34 : 1 = 0;
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int AMVOFFEN : 1;
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int EnAS0 : 1;
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int ADEn : 1;
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int HXEn : 1;
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int _reserved39 : 14 = 0;
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};
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static_assert(sizeof(Aarch64_SCR_EL3) == 8);
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struct Aarch64_SPSR_EL3 {
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enum Mode : uint16_t {
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EL0t = 0b0000,
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EL1t = 0b0100,
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EL1h = 0b0101,
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EL2t = 0b1000,
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EL2h = 0b1001,
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EL3t = 0b1100,
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EL3h = 0b1101
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};
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Mode M : 4;
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int M_4 : 1 = 0;
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int _reserved5 : 1 = 0;
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int F : 1;
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int I : 1;
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int A : 1;
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int D : 1;
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int _reserved10 : 10 = 0;
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int IL : 1;
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int SS : 1;
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int PAN : 1;
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int UA0 : 1;
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int _reserved24 : 4 = 0;
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int V : 1;
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int C : 1;
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int Z : 1;
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int N : 1;
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int _reserved32 : 32 = 0;
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};
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static_assert(sizeof(Aarch64_SPSR_EL3) == 8);
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}
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@ -12,8 +12,14 @@
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#include <Kernel/Prekernel/Arch/aarch64/UART.h>
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extern "C" [[noreturn]] void halt();
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extern "C" [[noreturn]] void init();
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extern "C" [[noreturn]] void os_start();
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static void set_up_el1_mode();
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static void set_up_el2_mode();
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static void set_up_el3_mode();
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[[noreturn]] static void switch_to_el1();
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extern "C" [[noreturn]] void init()
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{
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auto& uart = Prekernel::UART::the();
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@ -27,22 +33,11 @@ extern "C" [[noreturn]] void init()
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uart.print_num(firmware_version);
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uart.print_str("\r\n");
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auto exception_level = get_current_exception_level();
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uart.print_str("Current CPU exception level: EL");
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uart.print_num(exception_level);
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uart.print_str("\r\n");
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set_up_el3_mode();
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set_up_el2_mode();
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set_up_el1_mode();
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auto& timer = Prekernel::Timer::the();
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u64 start_musec = 0;
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for (;;) {
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u64 now_musec;
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while ((now_musec = timer.microseconds_since_boot()) - start_musec < 1'000'000)
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;
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start_musec = now_musec;
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uart.print_str("Timer: ");
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uart.print_num(now_musec);
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uart.print_str("\r\n");
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}
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switch_to_el1();
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}
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// FIXME: Share this with the Intel Prekernel.
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@ -66,3 +61,111 @@ void __stack_chk_fail()
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{
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halt();
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}
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static void set_up_el1_mode()
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{
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Kernel::Aarch64_SCTLR_EL1 sctlr_el1 = {};
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// Those bits are reserved on ARMv8.0
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sctlr_el1.LSMAOE = 1;
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sctlr_el1.nTLSMD = 1;
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sctlr_el1.SPAN = 1;
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sctlr_el1.IESB = 1;
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// Don't trap access to CTR_EL0
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sctlr_el1.UCT = 1;
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// Don't trap WFE instructions
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sctlr_el1.nTWE = 1;
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// Don't trap WFI instructions
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sctlr_el1.nTWI = 1;
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// Don't trap DC ZVA instructions
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sctlr_el1.DZE = 1;
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// Don't trap access to DAIF (debugging) flags of EFLAGS register
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sctlr_el1.UMA = 1;
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// Enable stack access alignment check for EL0
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sctlr_el1.SA0 = 1;
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// Enable stack access alignment check for EL1
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sctlr_el1.SA = 1;
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// Enable memory access alignment check
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sctlr_el1.A = 1;
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// Set the register
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asm("msr sctlr_el1, %[value]" ::[value] "r"(sctlr_el1));
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}
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static void set_up_el2_mode()
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{
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Kernel::Aarch64_HCR_EL2 hcr_el2 = {};
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// EL1 to use 64-bit mode
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hcr_el2.RW = 1;
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// Set the register
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asm("msr hcr_el2, %[value]" ::[value] "r"(hcr_el2));
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}
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static void set_up_el3_mode()
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{
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Kernel::Aarch64_SCR_EL3 scr_el3 = {};
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// Don't trap access to Counter-timer Physical Secure registers
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scr_el3.ST = 1;
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// Lower level to use Aarch64
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scr_el3.RW = 1;
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// Enable Hypervisor instructions at all levels
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scr_el3.HCE = 1;
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// Set the register
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asm("msr scr_el3, %[value]" ::[value] "r"(scr_el3));
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}
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[[noreturn]] static void switch_to_el1()
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{
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// Processor state to set when returned from this function (in new EL1 world)
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Kernel::Aarch64_SPSR_EL3 spsr_el3 = {};
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// Mask (disable) all interrupts
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spsr_el3.A = 1;
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spsr_el3.I = 1;
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spsr_el3.F = 1;
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// Indicate EL1 as exception origin mode (so we go back there)
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spsr_el3.M = Kernel::Aarch64_SPSR_EL3::Mode::EL1h;
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// Set the register
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asm("msr spsr_el3, %[value]" ::[value] "r"(spsr_el3));
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// This will jump into os_start() below, but in EL1
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return_from_el3();
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}
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extern "C" [[noreturn]] void os_start()
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{
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auto& uart = Prekernel::UART::the();
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auto exception_level = get_current_exception_level();
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uart.print_str("Current CPU exception level: EL");
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uart.print_num(exception_level);
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uart.print_str("\r\n");
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auto& timer = Prekernel::Timer::the();
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u64 start_musec = 0;
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for (;;) {
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u64 now_musec;
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while ((now_musec = timer.microseconds_since_boot()) - start_musec < 1'000'000)
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;
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start_musec = now_musec;
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uart.print_str("Timer: ");
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uart.print_num(now_musec);
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uart.print_str("\r\n");
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}
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}
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