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Kernel/aarch64: Implement tlb flushing

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This initial implementation flushes the complete tlb cache. A FIXME is
added to implement the partial tlb flushing.
This commit is contained in:
Timon Kruiper 2022-09-21 09:24:56 +02:00 committed by Andreas Kling
parent 424a974e01
commit 57901a6f62
2 changed files with 11 additions and 5 deletions
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11
Kernel/Arch/aarch64/Processor.cpp
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@ -41,7 +41,16 @@ void Processor::initialize(u32 cpu)
void Processor::flush_tlb_local(VirtualAddress, size_t)
{
// FIXME: Implement this
// FIXME: Figure out how to flush a single page
asm volatile("dsb ishst");
asm volatile("tlbi vmalle1is");
asm volatile("dsb ish");
asm volatile("isb");
}
void Processor::flush_tlb(Memory::PageDirectory const*, VirtualAddress vaddr, size_t page_count)
{
flush_tlb_local(vaddr, page_count);
}
}

5
Kernel/Arch/aarch64/Processor.h
View file

@ -77,10 +77,7 @@ public:
}
static void flush_tlb_local(VirtualAddress vaddr, size_t page_count);
ALWAYS_INLINE static void flush_tlb(Memory::PageDirectory const*, VirtualAddress const&, size_t)
{
VERIFY_NOT_REACHED();
}
static void flush_tlb(Memory::PageDirectory const*, VirtualAddress, size_t);
// FIXME: When aarch64 supports multiple cores, return the correct core id here.
ALWAYS_INLINE static u32 current_id()