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Kernel: Replace inline asm with typesafe static member functions
This commit is contained in:
James Mintram
Brian Gianforcaro
parent
4bc5936a57
commit
5a75bd31b0
4 changed files with 473 additions and 226 deletions
466
Kernel/Arch/aarch64/Aarch64Registers.h
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466
Kernel/Arch/aarch64/Aarch64Registers.h
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/*
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* Copyright (c) 2021, James Mintram <me@jamesrm.com>
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* Copyright (c) 2021, Marcin Undak <mcinek@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Types.h>
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namespace Kernel {
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/ID-AA64MMFR0-EL1--AArch64-Memory-Model-Feature-Register-0
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// Memory Model Feature Register 0
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struct Aarch64_ID_AA64MMFR0_EL1 {
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int PARange : 4;
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int ASIDBits : 4;
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int BigEnd : 4;
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int SNSMem : 4;
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int BigEndEL0 : 4;
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int TGran16 : 4;
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int TGran64 : 4;
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int TGran4 : 4;
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int TGran16_2 : 4;
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int TGran64_2 : 4;
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int TGran4_2 : 4;
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int ExS : 4;
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int RES0 : 8;
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int FGT : 4;
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int ECV : 4;
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static inline Aarch64_ID_AA64MMFR0_EL1 read()
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{
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Aarch64_ID_AA64MMFR0_EL1 feature_register;
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asm("mrs %[value], ID_AA64MMFR0_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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};
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1-
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// Translation Control Register
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struct Aarch64_TCR_EL1 {
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enum Shareability {
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NonSharable = 0b00,
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OuterShareable = 0b10,
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InnerShareable = 0b11,
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};
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enum OuterCacheability {
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NormalMemory_Outer_NonCacheable = 0b00,
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NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable = 0b01,
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NormalMemory_Outer_WriteThrough_ReadAllocate_NoWriteAllocateCacheable = 0b10,
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NormalMemory_Outer_WriteBack_ReadAllocate_NoWriteAllocateCacheable = 0b11,
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};
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enum InnerCacheability {
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NormalMemory_Inner_NonCacheable = 0b00,
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NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable = 0b01,
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NormalMemory_Inner_WriteThrough_ReadAllocate_NoWriteAllocateCacheable = 0b10,
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NormalMemory_Inner_WriteBack_ReadAllocate_NoWriteAllocateCacheable = 0b11,
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};
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// In AArch64, you have 3 possible translation granules to choose from,
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// each of which results in a different set of page sizes:
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// - 4KB granule: 4KB, 2MB, and 1GB pages.
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// - 16KB granule: 16KB and 32MB pages.
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// - 64KB granule: 64KB and 512MB pages.
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//
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// (https://stackoverflow.com/a/34269498)
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enum class TG1GranuleSize : int {
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Size_16KB = 0b01,
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Size_4KB = 0b10,
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Size_64KB = 0b11,
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};
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enum class TG0GranuleSize : int {
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Size_4KB = 0b00,
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Size_64KB = 0b01,
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Size_16KB = 0b10,
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};
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int T0SZ : 6;
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int RES0_0 : 1;
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int EPD0 : 1;
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InnerCacheability IRGN0 : 2;
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OuterCacheability ORGN0 : 2;
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Shareability SH0 : 2;
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TG0GranuleSize TG0 : 2;
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int T1SZ : 6;
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int A1 : 1;
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int EPD1 : 1;
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InnerCacheability IRGN1 : 2;
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OuterCacheability ORGN1 : 2;
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Shareability SH1 : 2;
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TG1GranuleSize TG1 : 2;
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int IPS : 3;
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int RES0_1 : 1;
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int AS : 1;
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int TBI0 : 1;
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int TBI1 : 1;
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int HA : 1;
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int HD : 1;
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int HPD0 : 1;
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int HPD1 : 1;
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int HWU059 : 1;
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int HWU060 : 1;
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int HWU061 : 1;
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int HWU062 : 1;
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int HWU159 : 1;
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int HWU160 : 1;
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int HWU161 : 1;
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int HWU162 : 1;
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int TBID0 : 1;
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int TBID1 : 1;
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int NFD0 : 1;
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int NFD1 : 1;
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int E0PD0 : 1;
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int E0PD1 : 1;
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int TCMA0 : 1;
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int TCMA1 : 1;
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int DS : 1;
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int RES0_2 : 4;
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static inline void write(Aarch64_TCR_EL1 tcr_el1)
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{
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asm("msr tcr_el1, %[value]" ::[value] "r"(tcr_el1));
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}
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static inline Aarch64_TCR_EL1 read()
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{
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Aarch64_TCR_EL1 tcr_el1;
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asm("mrs %[value], tcr_el1_el1"
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: [value] "=r"(tcr_el1));
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return tcr_el1;
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}
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static inline constexpr Aarch64_TCR_EL1 reset_value()
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{
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return {};
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}
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};
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static_assert(sizeof(Aarch64_TCR_EL1) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-03/AArch64-Registers/SCTLR-EL1--System-Control-Register--EL1-
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// System Control Register
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struct Aarch64_SCTLR_EL1 {
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int M : 1;
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int A : 1;
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int C : 1;
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int SA : 1;
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int SA0 : 1;
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int CP15BEN : 1;
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int _reserved6 : 1 = 0;
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int ITD : 1;
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int SED : 1;
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int UMA : 1;
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int _reserved10 : 1 = 0;
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int _reserved11 : 1 = 1;
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int I : 1;
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int EnDB : 1;
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int DZE : 1;
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int UCT : 1;
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int nTWI : 1;
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int _reserved17 : 1 = 0;
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int nTWE : 1;
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int WXN : 1;
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int _reserved20 : 1 = 1;
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int IESB : 1;
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int _reserved22 : 1 = 1;
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int SPAN : 1;
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int E0E : 1;
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int EE : 1;
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int UCI : 1;
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int EnDA : 1;
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int nTLSMD : 1;
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int LSMAOE : 1;
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int EnIB : 1;
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int EnIA : 1;
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int _reserved32 : 3 = 0;
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int BT0 : 1;
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int BT1 : 1;
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int ITFSB : 1;
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int TCF0 : 2;
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int TCF : 2;
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int ATA0 : 1;
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int ATA : 1;
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int DSSBS : 1;
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int TWEDEn : 1;
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int TWEDEL : 4;
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int _reserved50 : 4 = 0;
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int EnASR : 1;
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int EnAS0 : 1;
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int EnALS : 1;
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int EPAN : 1;
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int _reserved58 : 6 = 0;
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static inline void write(Aarch64_SCTLR_EL1 sctlr_el1)
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{
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asm("msr sctlr_el1, %[value]" ::[value] "r"(sctlr_el1));
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}
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static inline Aarch64_SCTLR_EL1 read()
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{
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Aarch64_SCTLR_EL1 sctlr;
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asm("mrs %[value], sctlr_el1"
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: [value] "=r"(sctlr));
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return sctlr;
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}
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static inline constexpr Aarch64_SCTLR_EL1 reset_value()
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{
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Aarch64_SCTLR_EL1 system_control_register_el1 = {};
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system_control_register_el1.LSMAOE = 1;
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system_control_register_el1.nTLSMD = 1;
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system_control_register_el1.SPAN = 1;
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system_control_register_el1.IESB = 1;
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return system_control_register_el1;
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}
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};
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static_assert(sizeof(Aarch64_SCTLR_EL1) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/HCR-EL2--Hypervisor-Configuration-Register
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// Hypervisor Configuration Register
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struct Aarch64_HCR_EL2 {
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int VM : 1;
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int SWIO : 1;
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int PTW : 1;
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int FMO : 1;
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int IMO : 1;
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int AMO : 1;
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int VF : 1;
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int VI : 1;
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int VSE : 1;
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int FB : 1;
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int BSU : 2;
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int DC : 1;
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int TWI : 1;
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int TWE : 1;
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int TID0 : 1;
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int TID1 : 1;
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int TID2 : 1;
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int TID3 : 1;
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int TSC : 1;
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int TIPDCP : 1;
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int TACR : 1;
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int TSW : 1;
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int TPCF : 1;
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int TPU : 1;
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int TTLB : 1;
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int TVM : 1;
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int TGE : 1;
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int TDZ : 1;
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int HCD : 1;
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int TRVM : 1;
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int RW : 1;
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int CD : 1;
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int ID : 1;
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int E2H : 1;
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int TLOR : 1;
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int TERR : 1;
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int MIOCNCE : 1;
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int _reserved39 : 1 = 0;
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int APK : 1 = 0;
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int API : 1 = 0;
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int NV : 1 = 0;
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int NV1 : 1 = 0;
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int AT : 1 = 0;
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int _reserved45 : 18 = 0;
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static inline void write(Aarch64_HCR_EL2 hcr_el2)
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{
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asm("msr hcr_el2, %[value]" ::[value] "r"(hcr_el2));
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}
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static inline Aarch64_HCR_EL2 read()
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{
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Aarch64_HCR_EL2 spsr;
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asm("mrs %[value], hcr_el2"
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: [value] "=r"(spsr));
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return spsr;
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}
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};
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static_assert(sizeof(Aarch64_HCR_EL2) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/SCR-EL3--Secure-Configuration-Register
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// Secure Configuration Register
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struct Aarch64_SCR_EL3 {
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int NS : 1;
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int IRQ : 1;
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int FIQ : 1;
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int EA : 1;
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int _reserved4 : 1 = 1;
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int _reserved5 : 1 = 1;
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int _reserved6 : 1 = 0;
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int SMD : 1;
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int HCE : 1;
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int SIF : 1;
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int RW : 1;
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int ST : 1;
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int TWI : 1;
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int TWE : 1;
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int TLOR : 1;
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int TERR : 1;
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int APK : 1;
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int API : 1;
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int EEL2 : 1;
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int EASE : 1;
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int NMEA : 1;
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int FIEN : 1;
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int _reserved22 : 3 = 0;
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int EnSCXT : 1;
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int ATA : 1;
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int FGTEn : 1;
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int ECVEn : 1;
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int TWEDEn : 1;
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int TWEDEL : 4;
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int _reserved34 : 1 = 0;
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int AMVOFFEN : 1;
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int EnAS0 : 1;
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int ADEn : 1;
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int HXEn : 1;
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int _reserved39 : 14 = 0;
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static inline void write(Aarch64_SCR_EL3 scr_el3)
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{
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asm("msr scr_el3, %[value]" ::[value] "r"(scr_el3));
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}
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static inline Aarch64_SCR_EL3 read()
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{
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Aarch64_SCR_EL3 scr;
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asm("mrs %[value], scr_el3"
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: [value] "=r"(scr));
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return scr;
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}
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};
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static_assert(sizeof(Aarch64_SCR_EL3) == 8);
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struct Aarch64_SPSR_EL2 {
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enum Mode : u16 {
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EL0t = 0b0000,
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EL1t = 0b0100,
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EL1h = 0b0101,
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EL2t = 0b1000,
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EL2h = 0b1001
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};
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Mode M : 4;
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int M_4 : 1 = 0;
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int _reserved5 : 1 = 0;
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int F : 1;
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int I : 1;
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int A : 1;
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int D : 1;
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int BTYPE : 2;
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int SSBS : 1;
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int _reserved13 : 7 = 0;
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int IL : 1;
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int SS : 1;
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int PAN : 1;
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int UA0 : 1;
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int DIT : 1;
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int TCO : 1;
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int _reserved26 : 2 = 0;
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int V : 1;
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int C : 1;
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int Z : 1;
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int N : 1;
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int _reserved32 : 32 = 0;
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static inline void write(Aarch64_SPSR_EL2 spsr_el2)
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{
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asm("msr spsr_el2, %[value]" ::[value] "r"(spsr_el2));
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}
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static inline Aarch64_SPSR_EL2 read()
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{
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Aarch64_SPSR_EL2 spsr;
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asm("mrs %[value], spsr_el2"
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: [value] "=r"(spsr));
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return spsr;
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}
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};
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static_assert(sizeof(Aarch64_SPSR_EL2) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/SPSR-EL3--Saved-Program-Status-Register--EL3-
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// Saved Program Status Register
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struct Aarch64_SPSR_EL3 {
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enum Mode : uint16_t {
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EL0t = 0b0000,
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EL1t = 0b0100,
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EL1h = 0b0101,
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EL2t = 0b1000,
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EL2h = 0b1001,
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EL3t = 0b1100,
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EL3h = 0b1101
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};
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Mode M : 4;
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int M_4 : 1 = 0;
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int _reserved5 : 1 = 0;
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int F : 1;
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int I : 1;
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int A : 1;
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int D : 1;
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int _reserved10 : 10 = 0;
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int IL : 1;
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int SS : 1;
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int PAN : 1;
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int UA0 : 1;
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int _reserved24 : 4 = 0;
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int V : 1;
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int C : 1;
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int Z : 1;
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int N : 1;
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int _reserved32 : 32 = 0;
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static inline void write(Aarch64_SPSR_EL3 spsr_el3)
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{
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asm("msr spsr_el3, %[value]" ::[value] "r"(spsr_el3));
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}
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static inline Aarch64_SPSR_EL3 read()
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{
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Aarch64_SPSR_EL3 spsr;
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asm("mrs %[value], spsr_el3"
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: [value] "=r"(spsr));
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return spsr;
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}
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};
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static_assert(sizeof(Aarch64_SPSR_EL3) == 8);
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// https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/MAIR-EL1--Memory-Attribute-Indirection-Register--EL1-?lang=en#fieldset_0-63_0
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// Memory Attribute Indirection Register
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struct Aarch64_MAIR_EL1 {
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using AttributeEncoding = uint8_t;
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AttributeEncoding Attr[8];
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static inline void write(Aarch64_MAIR_EL1 mair_el1)
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{
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asm("msr mair_el1, %[value]" ::[value] "r"(mair_el1));
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}
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};
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static_assert(sizeof(Aarch64_MAIR_EL1) == 8);
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}
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@ -1,215 +0,0 @@
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/*
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* Copyright (c) 2021, Marcin Undak <mcinek@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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namespace Kernel {
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struct Aarch64_SCTLR_EL1 {
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int M : 1;
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int A : 1;
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int C : 1;
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int SA : 1;
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int SA0 : 1;
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int CP15BEN : 1;
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int _reserved6 : 1 = 0;
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int ITD : 1;
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int SED : 1;
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int UMA : 1;
|
||||
int _reserved10 : 1 = 0;
|
||||
int _reserved11 : 1 = 1;
|
||||
int I : 1;
|
||||
int EnDB : 1;
|
||||
int DZE : 1;
|
||||
int UCT : 1;
|
||||
int nTWI : 1;
|
||||
int _reserved17 : 1 = 0;
|
||||
int nTWE : 1;
|
||||
int WXN : 1;
|
||||
int _reserved20 : 1 = 1;
|
||||
int IESB : 1;
|
||||
int _reserved22 : 1 = 1;
|
||||
int SPAN : 1;
|
||||
int E0E : 1;
|
||||
int EE : 1;
|
||||
int UCI : 1;
|
||||
int EnDA : 1;
|
||||
int nTLSMD : 1;
|
||||
int LSMAOE : 1;
|
||||
int EnIB : 1;
|
||||
int EnIA : 1;
|
||||
int _reserved32 : 3 = 0;
|
||||
int BT0 : 1;
|
||||
int BT1 : 1;
|
||||
int ITFSB : 1;
|
||||
int TCF0 : 2;
|
||||
int TCF : 2;
|
||||
int ATA0 : 1;
|
||||
int ATA : 1;
|
||||
int DSSBS : 1;
|
||||
int TWEDEn : 1;
|
||||
int TWEDEL : 4;
|
||||
int _reserved50 : 4 = 0;
|
||||
int EnASR : 1;
|
||||
int EnAS0 : 1;
|
||||
int EnALS : 1;
|
||||
int EPAN : 1;
|
||||
int _reserved58 : 6 = 0;
|
||||
};
|
||||
static_assert(sizeof(Aarch64_SCTLR_EL1) == 8);
|
||||
|
||||
struct Aarch64_HCR_EL2 {
|
||||
int VM : 1;
|
||||
int SWIO : 1;
|
||||
int PTW : 1;
|
||||
int FMO : 1;
|
||||
int IMO : 1;
|
||||
int AMO : 1;
|
||||
int VF : 1;
|
||||
int VI : 1;
|
||||
int VSE : 1;
|
||||
int FB : 1;
|
||||
int BSU : 2;
|
||||
int DC : 1;
|
||||
int TWI : 1;
|
||||
int TWE : 1;
|
||||
int TID0 : 1;
|
||||
int TID1 : 1;
|
||||
int TID2 : 1;
|
||||
int TID3 : 1;
|
||||
int TSC : 1;
|
||||
int TIPDCP : 1;
|
||||
int TACR : 1;
|
||||
int TSW : 1;
|
||||
int TPCF : 1;
|
||||
int TPU : 1;
|
||||
int TTLB : 1;
|
||||
int TVM : 1;
|
||||
int TGE : 1;
|
||||
int TDZ : 1;
|
||||
int HCD : 1;
|
||||
int TRVM : 1;
|
||||
int RW : 1;
|
||||
int CD : 1;
|
||||
int ID : 1;
|
||||
int E2H : 1;
|
||||
int TLOR : 1;
|
||||
int TERR : 1;
|
||||
int MIOCNCE : 1;
|
||||
int _reserved39 : 1 = 0;
|
||||
int APK : 1 = 0;
|
||||
int API : 1 = 0;
|
||||
int NV : 1 = 0;
|
||||
int NV1 : 1 = 0;
|
||||
int AT : 1 = 0;
|
||||
int _reserved45 : 18 = 0;
|
||||
};
|
||||
static_assert(sizeof(Aarch64_HCR_EL2) == 8);
|
||||
|
||||
struct Aarch64_SCR_EL3 {
|
||||
int NS : 1;
|
||||
int IRQ : 1;
|
||||
int FIQ : 1;
|
||||
int EA : 1;
|
||||
int _reserved4 : 1 = 1;
|
||||
int _reserved5 : 1 = 1;
|
||||
int _reserved6 : 1 = 0;
|
||||
int SMD : 1;
|
||||
int HCE : 1;
|
||||
int SIF : 1;
|
||||
int RW : 1;
|
||||
int ST : 1;
|
||||
int TWI : 1;
|
||||
int TWE : 1;
|
||||
int TLOR : 1;
|
||||
int TERR : 1;
|
||||
int APK : 1;
|
||||
int API : 1;
|
||||
int EEL2 : 1;
|
||||
int EASE : 1;
|
||||
int NMEA : 1;
|
||||
int FIEN : 1;
|
||||
int _reserved22 : 3 = 0;
|
||||
int EnSCXT : 1;
|
||||
int ATA : 1;
|
||||
int FGTEn : 1;
|
||||
int ECVEn : 1;
|
||||
int TWEDEn : 1;
|
||||
int TWEDEL : 4;
|
||||
int _reserved34 : 1 = 0;
|
||||
int AMVOFFEN : 1;
|
||||
int EnAS0 : 1;
|
||||
int ADEn : 1;
|
||||
int HXEn : 1;
|
||||
int _reserved39 : 14 = 0;
|
||||
};
|
||||
static_assert(sizeof(Aarch64_SCR_EL3) == 8);
|
||||
|
||||
struct Aarch64_SPSR_EL2 {
|
||||
enum Mode : uint16_t {
|
||||
EL0t = 0b0000,
|
||||
EL1t = 0b0100,
|
||||
EL1h = 0b0101,
|
||||
EL2t = 0b1000,
|
||||
EL2h = 0b1001
|
||||
};
|
||||
|
||||
Mode M : 4;
|
||||
int M_4 : 1 = 0;
|
||||
int _reserved5 : 1 = 0;
|
||||
int F : 1;
|
||||
int I : 1;
|
||||
int A : 1;
|
||||
int D : 1;
|
||||
int BTYPE : 2;
|
||||
int SSBS : 1;
|
||||
int _reserved13 : 7 = 0;
|
||||
int IL : 1;
|
||||
int SS : 1;
|
||||
int PAN : 1;
|
||||
int UA0 : 1;
|
||||
int DIT : 1;
|
||||
int TCO : 1;
|
||||
int _reserved26 : 2 = 0;
|
||||
int V : 1;
|
||||
int C : 1;
|
||||
int Z : 1;
|
||||
int N : 1;
|
||||
int _reserved32 : 32 = 0;
|
||||
};
|
||||
static_assert(sizeof(Aarch64_SPSR_EL2) == 8);
|
||||
|
||||
struct Aarch64_SPSR_EL3 {
|
||||
enum Mode : uint16_t {
|
||||
EL0t = 0b0000,
|
||||
EL1t = 0b0100,
|
||||
EL1h = 0b0101,
|
||||
EL2t = 0b1000,
|
||||
EL2h = 0b1001,
|
||||
EL3t = 0b1100,
|
||||
EL3h = 0b1101
|
||||
};
|
||||
|
||||
Mode M : 4;
|
||||
int M_4 : 1 = 0;
|
||||
int _reserved5 : 1 = 0;
|
||||
int F : 1;
|
||||
int I : 1;
|
||||
int A : 1;
|
||||
int D : 1;
|
||||
int _reserved10 : 10 = 0;
|
||||
int IL : 1;
|
||||
int SS : 1;
|
||||
int PAN : 1;
|
||||
int UA0 : 1;
|
||||
int _reserved24 : 4 = 0;
|
||||
int V : 1;
|
||||
int C : 1;
|
||||
int Z : 1;
|
||||
int N : 1;
|
||||
int _reserved32 : 32 = 0;
|
||||
};
|
||||
static_assert(sizeof(Aarch64_SPSR_EL3) == 8);
|
||||
}
|
||||
|
|
@ -6,6 +6,7 @@
|
|||
*/
|
||||
|
||||
#include <AK/Types.h>
|
||||
#include <Kernel/Arch/aarch64/Aarch64Registers.h>
|
||||
#include <Kernel/Prekernel/Arch/aarch64/Aarch64_asm_utils.h>
|
||||
#include <Kernel/Prekernel/Arch/aarch64/BootPPMParser.h>
|
||||
#include <Kernel/Prekernel/Arch/aarch64/Framebuffer.h>
|
||||
|
|
@ -140,8 +141,7 @@ static void set_up_el1_mode()
|
|||
// Enable memory access alignment check
|
||||
system_control_register_el1.A = 1;
|
||||
|
||||
// Set the register
|
||||
asm("msr sctlr_el1, %[value]" ::[value] "r"(system_control_register_el1));
|
||||
Kernel::Aarch64_SCTLR_EL1::write(system_control_register_el1);
|
||||
}
|
||||
|
||||
static void set_up_el2_mode()
|
||||
|
|
@ -151,8 +151,7 @@ static void set_up_el2_mode()
|
|||
// EL1 to use 64-bit mode
|
||||
hypervisor_configuration_register_el2.RW = 1;
|
||||
|
||||
// Set the register
|
||||
asm("msr hcr_el2, %[value]" ::[value] "r"(hypervisor_configuration_register_el2));
|
||||
Kernel::Aarch64_HCR_EL2::write(hypervisor_configuration_register_el2);
|
||||
}
|
||||
|
||||
static void set_up_el3_mode()
|
||||
|
|
@ -168,8 +167,7 @@ static void set_up_el3_mode()
|
|||
// Enable Hypervisor instructions at all levels
|
||||
secure_configuration_register_el3.HCE = 1;
|
||||
|
||||
// Set the register
|
||||
asm("msr scr_el3, %[value]" ::[value] "r"(secure_configuration_register_el3));
|
||||
Kernel::Aarch64_SCR_EL3::write(secure_configuration_register_el3);
|
||||
}
|
||||
|
||||
[[noreturn]] static void jump_to_os_start_from_el2()
|
||||
|
|
@ -185,8 +183,7 @@ static void set_up_el3_mode()
|
|||
// Indicate EL1 as exception origin mode (so we go back there)
|
||||
saved_program_status_register_el2.M = Kernel::Aarch64_SPSR_EL2::Mode::EL1h;
|
||||
|
||||
// Set the register
|
||||
asm("msr spsr_el2, %[value]" ::[value] "r"(saved_program_status_register_el2));
|
||||
Kernel::Aarch64_SPSR_EL2::write(saved_program_status_register_el2);
|
||||
|
||||
// This will jump into os_start()
|
||||
return_from_el2();
|
||||
|
|
@ -205,8 +202,7 @@ static void set_up_el3_mode()
|
|||
// Indicate EL1 as exception origin mode (so we go back there)
|
||||
saved_program_status_register_el3.M = Kernel::Aarch64_SPSR_EL3::Mode::EL1h;
|
||||
|
||||
// Set the register
|
||||
asm("msr spsr_el3, %[value]" ::[value] "r"(saved_program_status_register_el3));
|
||||
Kernel::Aarch64_SPSR_EL3::write(saved_program_status_register_el3);
|
||||
|
||||
// This will jump into os_start() below
|
||||
return_from_el3();
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@ set(SOURCES
|
|||
if ("${SERENITY_ARCH}" STREQUAL "aarch64")
|
||||
set(SOURCES
|
||||
${SOURCES}
|
||||
Arch/aarch64/Aarch64_asm_utils.S
|
||||
Arch/aarch64/BootPPMParser.cpp
|
||||
Arch/aarch64/GPIO.cpp
|
||||
Arch/aarch64/Framebuffer.cpp
|
||||
|
|
@ -15,6 +14,7 @@ if ("${SERENITY_ARCH}" STREQUAL "aarch64")
|
|||
Arch/aarch64/Timer.cpp
|
||||
Arch/aarch64/UART.cpp
|
||||
Arch/aarch64/Utils.cpp
|
||||
Arch/aarch64/Aarch64_asm_utils.S
|
||||
Arch/aarch64/boot.S
|
||||
Arch/aarch64/init.cpp
|
||||
)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue