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https://github.com/SerenityOS/serenity.git
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Kernel: Add support for the RTL8168E-VL variant to the RTL8168 driver
Specifically chip version 17.
This commit is contained in:
Luke
Andreas Kling
parent
a898e01d4d
commit
d2f1476428
2 changed files with 172 additions and 4 deletions
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@ -107,6 +107,7 @@ namespace Kernel {
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#define CFG3_READY_TO_L23 0x2
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#define CFG5_ASPM_ENABLE 0x1
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#define CFG5_SPI_ENABLE 0x8
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#define PHY_LINK_STATUS 0x2
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@ -167,6 +168,7 @@ namespace Kernel {
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#define MTPS_JUMBO 0x3F
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#define MISC_RXDV_GATE_ENABLE 0x80000
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#define MISC_PWM_ENABLE 0x400000
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#define MISC2_PFM_D3COLD_ENABLE 0x40
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@ -197,7 +199,7 @@ UNMAP_AFTER_INIT RTL8168NetworkAdapter::RTL8168NetworkAdapter(PCI::Address addre
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identify_chip_version();
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dmesgln("RTL8168: Version detected - {} ({}{})", possible_device_name(), (u8)m_version, m_version_uncertain ? "?" : "");
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if (m_version == ChipVersion::Unknown || m_version >= ChipVersion::Version4) {
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if (m_version == ChipVersion::Unknown || (m_version >= ChipVersion::Version4 && m_version <= ChipVersion::Version16) || m_version >= ChipVersion::Version18) {
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dmesgln("RTL8168: Aborting initialization! Support for your chip version ({}) is not implemented yet, please open a GH issue and include this message.", (u8)m_version);
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return; // Each ChipVersion requires a specific implementation of configure_phy and hardware_quirks
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}
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@ -384,8 +386,10 @@ void RTL8168NetworkAdapter::configure_phy()
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TODO();
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case ChipVersion::Version16:
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TODO();
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case ChipVersion::Version17:
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TODO();
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case ChipVersion::Version17: {
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configure_phy_e_2();
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return;
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}
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case ChipVersion::Version18:
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TODO();
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case ChipVersion::Version19:
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@ -445,6 +449,93 @@ void RTL8168NetworkAdapter::configure_phy_b_2()
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phy_out_batch(phy_registers, 3);
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}
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void RTL8168NetworkAdapter::configure_phy_e_2()
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{
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// FIXME: linux's driver writes a firmware blob to the device at this point, is this needed?
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constexpr PhyRegister phy_registers[] = {
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// Enable delay cap
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{ 0x1f, 0x4 },
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{ 0x1f, 0x7 },
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{ 0x1e, 0xac },
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{ 0x18, 0x6 },
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{ 0x1f, 0x2 },
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{ 0x1f, 0 },
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{ 0x1f, 0 },
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// Channel estimation fine tune
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{ 0x1f, 0x3 },
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{ 0x9, 0xa20f },
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{ 0x1f, 0 },
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{ 0x1f, 0 },
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// Green Setting
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{ 0x1f, 0x5 },
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{ 0x5, 0x8b5b },
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{ 0x6, 0x9222 },
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{ 0x5, 0x8b6d },
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{ 0x6, 0x8000 },
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{ 0x5, 0x8b76 },
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{ 0x6, 0x8000 },
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{ 0x1f, 0 },
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};
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phy_out_batch(phy_registers, 19);
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// 4 corner performance improvement
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phy_out(0x1f, 0x5);
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phy_out(0x5, 0x8b80);
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phy_update(0x17, 0x6, 0);
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phy_out(0x1f, 0);
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// PHY auto speed down
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phy_out(0x1f, 0x4);
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phy_out(0x1f, 0x7);
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phy_out(0x1e, 0x2d);
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phy_update(0x18, 0x10, 0);
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phy_out(0x1f, 0x2);
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phy_out(0x1f, 0);
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phy_update(0x14, 0x8000, 0);
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// Improve 10M EEE waveform
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phy_out(0x1f, 0x5);
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phy_out(0x5, 0x8b86);
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phy_update(0x6, 0x1, 0);
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phy_out(0x1f, 0);
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// Improve 2-pair detection performance
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phy_out(0x1f, 0x5);
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phy_out(0x5, 0x8b85);
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phy_update(0x6, 0x4000, 0);
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phy_out(0x1f, 0);
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// EEE Setting
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eri_update(0x1b0, ERI_MASK_1111, 0, 0x3, ERI_EXGMAC);
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phy_out(0x1f, 0x5);
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phy_out(0x5, 0x8b85);
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phy_update(0x6, 0, 0x2000);
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phy_out(0x1f, 0x4);
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phy_out(0x1f, 0x7);
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phy_out(0x1e, 0x20);
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phy_update(0x15, 0, 0x100);
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phy_out(0x1f, 0x2);
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phy_out(0x1f, 0);
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phy_out(0xd, 0x7);
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phy_out(0xe, 0x3c);
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phy_out(0xd, 0x4007);
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phy_out(0xe, 0);
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phy_out(0xd, 0);
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// Green feature
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phy_out(0x1f, 0x3);
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phy_update(0x19, 0, 0x1);
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phy_update(0x10, 0, 0x400);
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phy_out(0x1f, 0);
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// Broken BIOS workaround: feed GigaMAC registers with MAC address.
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rar_exgmac_set();
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}
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void RTL8168NetworkAdapter::configure_phy_h_1()
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{
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// FIXME: linux's driver writes a firmware blob to the device at this point, is this needed?
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@ -620,6 +711,25 @@ void RTL8168NetworkAdapter::configure_phy_h_2()
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phy_out(0x1f, 0);
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}
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void RTL8168NetworkAdapter::rar_exgmac_set()
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{
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auto mac = mac_address();
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const u16 w[] = {
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(u16)(mac[0] | (mac[1] << 8)),
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(u16)(mac[2] | (mac[3] << 8)),
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(u16)(mac[4] | (mac[5] << 8)),
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};
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const ExgMacRegister exg_mac_registers[] = {
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{ 0xe0, ERI_MASK_1111, (u32)(w[0] | (w[1] << 16)) },
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{ 0xe4, ERI_MASK_1111, (u32)w[2] },
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{ 0xf0, ERI_MASK_1111, (u32)(w[0] << 16) },
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{ 0xf4, ERI_MASK_1111, (u32)(w[1] | (w[2] << 16)) },
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};
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exgmac_out_batch(exg_mac_registers, 4);
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}
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void RTL8168NetworkAdapter::start_hardware()
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{
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@ -709,7 +819,8 @@ void RTL8168NetworkAdapter::hardware_quirks()
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case ChipVersion::Version16:
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TODO();
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case ChipVersion::Version17:
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TODO();
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hardware_quirks_e_2();
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return;
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case ChipVersion::Version18:
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TODO();
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case ChipVersion::Version19:
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@ -760,6 +871,46 @@ void RTL8168NetworkAdapter::hardware_quirks_b_2()
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out8(REG_CONFIG4, in8(REG_CONFIG4) & ~1);
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}
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void RTL8168NetworkAdapter::hardware_quirks_e_2()
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{
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constexpr EPhyUpdate ephy_info[] = {
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{ 0x9, 0, 0x80 },
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{ 0x19, 0, 0x224 },
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};
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csi_enable(CSI_ACCESS_1);
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extended_phy_initialize(ephy_info, 2);
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// FIXME: MTU performance tweak
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eri_out(0xc0, ERI_MASK_0011, 0, ERI_EXGMAC);
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eri_out(0xb8, ERI_MASK_0011, 0, ERI_EXGMAC);
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eri_out(0xc8, ERI_MASK_1111, 0x100002, ERI_EXGMAC);
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eri_out(0xe8, ERI_MASK_1111, 0x100006, ERI_EXGMAC);
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eri_out(0xcc, ERI_MASK_1111, 0x50, ERI_EXGMAC);
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eri_out(0xd0, ERI_MASK_1111, 0x7ff0060, ERI_EXGMAC);
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eri_update(0x1b0, ERI_MASK_0001, 0x10, 0, ERI_EXGMAC);
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eri_update(0xd4, ERI_MASK_0011, 0xc00, 0xff00, ERI_EXGMAC);
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// Set early TX
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out8(REG_MTPS, 0x27);
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// FIXME: Disable PCIe clock request
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// enable tx auto fifo
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out32(REG_TXCFG, in32(REG_TXCFG) | TXCFG_AUTO_FIFO);
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out8(REG_MCU, in8(REG_MCU) & ~MCU_NOW_IS_OOB);
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// Set EEE LED frequency
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out8(REG_EEE_LED, in8(REG_EEE_LED) & ~0x7);
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out8(REG_DLLPR, in8(REG_DLLPR) | DLLPR_PFM_ENABLE);
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out32(REG_MISC, in32(REG_MISC) | MISC_PWM_ENABLE);
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out8(REG_CONFIG5, in8(REG_CONFIG5) & ~CFG5_SPI_ENABLE);
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}
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void RTL8168NetworkAdapter::hardware_quirks_h()
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{
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// disable aspm and clock request before accessing extended phy
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@ -1189,6 +1340,13 @@ void RTL8168NetworkAdapter::eri_update(u32 address, u32 mask, u32 set, u32 clear
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eri_out(address, mask, (value & ~clear) | set, type);
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}
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void RTL8168NetworkAdapter::exgmac_out_batch(const ExgMacRegister exgmac_registers[], size_t length)
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{
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for (size_t i = 0; i < length; i++) {
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eri_out(exgmac_registers[i].address, exgmac_registers[i].mask, exgmac_registers[i].value, ERI_EXGMAC);
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}
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}
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void RTL8168NetworkAdapter::csi_out(u32 address, u32 data)
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{
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VERIFY(m_version >= ChipVersion::Version4);
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@ -128,12 +128,16 @@ private:
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void configure_phy();
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void configure_phy_b_1();
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void configure_phy_b_2();
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void configure_phy_e_2();
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void configure_phy_h_1();
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void configure_phy_h_2();
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void rar_exgmac_set();
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void hardware_quirks();
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void hardware_quirks_b_1();
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void hardware_quirks_b_2();
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void hardware_quirks_e_2();
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void hardware_quirks_h();
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void initialize_rx_descriptors();
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@ -170,6 +174,12 @@ private:
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void eri_out(u32 address, u32 mask, u32 data, u32 type);
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u32 eri_in(u32 address, u32 type);
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void eri_update(u32 address, u32 mask, u32 set, u32 clear, u32 type);
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struct ExgMacRegister {
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u16 address;
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u16 mask;
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u32 value;
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};
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void exgmac_out_batch(const ExgMacRegister[], size_t length);
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void csi_out(u32 address, u32 data);
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u32 csi_in(u32 address);
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