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https://github.com/SerenityOS/serenity.git
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2718d7c74c
Also handle native and compatibility channel modes together, so if only one IDE channel was set to work on PCI native mode, we need to handle it separately, so the other channel continue to operate with the legacy IO ports and interrupt line.
211 lines
8 KiB
C++
211 lines
8 KiB
C++
/*
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* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <AK/OwnPtr.h>
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#include <AK/RefPtr.h>
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#include <AK/Types.h>
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#include <Kernel/FileSystem/ProcFS.h>
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#include <Kernel/Storage/BMIDEChannel.h>
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#include <Kernel/Storage/IDEController.h>
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#include <Kernel/Storage/PATADiskDevice.h>
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namespace Kernel {
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UNMAP_AFTER_INIT NonnullRefPtr<IDEController> IDEController::initialize(PCI::Address address, bool force_pio)
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{
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return adopt(*new IDEController(address, force_pio));
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}
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bool IDEController::reset()
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{
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TODO();
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}
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bool IDEController::shutdown()
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{
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TODO();
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}
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size_t IDEController::devices_count() const
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{
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size_t count = 0;
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for (u32 index = 0; index < 4; index++) {
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if (!device(index).is_null())
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count++;
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}
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return count;
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}
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void IDEController::start_request(const StorageDevice&, AsyncBlockDeviceRequest&)
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{
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VERIFY_NOT_REACHED();
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}
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void IDEController::complete_current_request(AsyncDeviceRequest::RequestResult)
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{
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VERIFY_NOT_REACHED();
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}
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UNMAP_AFTER_INIT IDEController::IDEController(PCI::Address address, bool force_pio)
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: StorageController()
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, PCI::DeviceController(address)
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{
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initialize(force_pio);
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}
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UNMAP_AFTER_INIT IDEController::~IDEController()
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{
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}
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bool IDEController::is_pci_native_mode_enabled() const
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{
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return (PCI::get_programming_interface(pci_address()) & 0x05) != 0;
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}
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bool IDEController::is_pci_native_mode_enabled_on_primary_channel() const
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{
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return (PCI::get_programming_interface(pci_address()) & 0x1) == 0x1;
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}
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bool IDEController::is_pci_native_mode_enabled_on_secondary_channel() const
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{
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return (PCI::get_programming_interface(pci_address()) & 0x4) == 0x4;
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}
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bool IDEController::is_bus_master_capable() const
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{
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return PCI::get_programming_interface(pci_address()) & (1 << 7);
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}
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static const char* detect_controller_type(u8 programming_value)
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{
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switch (programming_value) {
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case 0x00:
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return "ISA Compatibility mode-only controller";
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case 0x05:
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return "PCI native mode-only controller";
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case 0x0A:
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return "ISA Compatibility mode controller, supports both channels switched to PCI native mode";
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case 0x0F:
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return "PCI native mode controller, supports both channels switched to ISA compatibility mode";
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case 0x80:
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return "ISA Compatibility mode-only controller, supports bus mastering";
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case 0x85:
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return "PCI native mode-only controller, supports bus mastering";
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case 0x8A:
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return "ISA Compatibility mode controller, supports both channels switched to PCI native mode, supports bus mastering";
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case 0x8F:
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return "PCI native mode controller, supports both channels switched to ISA compatibility mode, supports bus mastering";
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default:
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VERIFY_NOT_REACHED();
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}
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VERIFY_NOT_REACHED();
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}
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UNMAP_AFTER_INIT void IDEController::initialize(bool force_pio)
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{
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auto bus_master_base = IOAddress(PCI::get_BAR4(pci_address()) & (~1));
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dbgln("IDE controller @ {}: bus master base was set to {}", pci_address(), bus_master_base);
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dbgln("IDE controller @ {}: interrupt line was set to {}", pci_address(), PCI::get_interrupt_line(pci_address()));
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dbgln("IDE controller @ {}: {}", pci_address(), detect_controller_type(PCI::get_programming_interface(pci_address())));
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dbgln("IDE controller @ {}: primary channel DMA capable? {}", pci_address(), ((bus_master_base.offset(2).in<u8>() >> 5) & 0b11));
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dbgln("IDE controller @ {}: secondary channel DMA capable? {}", pci_address(), ((bus_master_base.offset(2 + 8).in<u8>() >> 5) & 0b11));
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if (!is_bus_master_capable())
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force_pio = true;
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auto bar0 = PCI::get_BAR0(pci_address());
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auto primary_base_io = (bar0 == 0x1 || bar0 == 0) ? IOAddress(0x1F0) : IOAddress(bar0 & (~1));
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auto bar1 = PCI::get_BAR1(pci_address());
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auto primary_control_io = (bar1 == 0x1 || bar1 == 0) ? IOAddress(0x3F6) : IOAddress(bar1 & (~1));
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auto bar2 = PCI::get_BAR2(pci_address());
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auto secondary_base_io = (bar2 == 0x1 || bar2 == 0) ? IOAddress(0x170) : IOAddress(bar2 & (~1));
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auto bar3 = PCI::get_BAR3(pci_address());
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auto secondary_control_io = (bar3 == 0x1 || bar3 == 0) ? IOAddress(0x376) : IOAddress(bar3 & (~1));
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auto irq_line = PCI::get_interrupt_line(pci_address());
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if (is_pci_native_mode_enabled()) {
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VERIFY(irq_line != 0);
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}
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if (is_pci_native_mode_enabled_on_primary_channel()) {
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if (force_pio)
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m_channels.append(IDEChannel::create(*this, irq_line, { primary_base_io, primary_control_io }, IDEChannel::ChannelType::Primary));
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else
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m_channels.append(BMIDEChannel::create(*this, irq_line, { primary_control_io, primary_control_io, bus_master_base }, IDEChannel::ChannelType::Primary));
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} else {
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if (force_pio)
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m_channels.append(IDEChannel::create(*this, { primary_base_io, primary_control_io }, IDEChannel::ChannelType::Primary));
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else
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m_channels.append(BMIDEChannel::create(*this, { primary_base_io, primary_control_io, bus_master_base }, IDEChannel::ChannelType::Primary));
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}
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m_channels[0].enable_irq();
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if (is_pci_native_mode_enabled_on_secondary_channel()) {
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if (force_pio)
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m_channels.append(IDEChannel::create(*this, irq_line, { secondary_base_io, secondary_control_io }, IDEChannel::ChannelType::Secondary));
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else
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m_channels.append(BMIDEChannel::create(*this, irq_line, { secondary_base_io, secondary_control_io, bus_master_base.offset(8) }, IDEChannel::ChannelType::Secondary));
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} else {
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if (force_pio)
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m_channels.append(IDEChannel::create(*this, { secondary_base_io, secondary_control_io }, IDEChannel::ChannelType::Secondary));
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else
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m_channels.append(BMIDEChannel::create(*this, { secondary_base_io, secondary_control_io, bus_master_base.offset(8) }, IDEChannel::ChannelType::Secondary));
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}
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m_channels[1].enable_irq();
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}
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RefPtr<StorageDevice> IDEController::device_by_channel_and_position(u32 index) const
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{
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switch (index) {
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case 0:
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return m_channels[0].master_device();
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case 1:
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return m_channels[0].slave_device();
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case 2:
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return m_channels[1].master_device();
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case 3:
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return m_channels[1].slave_device();
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}
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VERIFY_NOT_REACHED();
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}
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RefPtr<StorageDevice> IDEController::device(u32 index) const
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{
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NonnullRefPtrVector<StorageDevice> connected_devices;
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for (size_t index = 0; index < 4; index++) {
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auto checked_device = device_by_channel_and_position(index);
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if (checked_device.is_null())
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continue;
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connected_devices.append(checked_device.release_nonnull());
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}
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if (index >= connected_devices.size())
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return nullptr;
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return connected_devices[index];
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}
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}
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