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authorAndrew Lee <alee14498@protonmail.com>2021-08-15 00:34:05 -0400
committerAndrew Lee <alee14498@protonmail.com>2021-08-15 00:34:05 -0400
commit60cc83bf91bfc9bb02f6304b5d6c8234ba6d210f (patch)
treefdc0be85a1ca35e34c3ae2c805fe9b718e3c1091 /gcc-1.40/gcc.aux
parentdd8dfab51b832a654365ed00c06bf802ff628bfa (diff)
downloadlinux-0.01-distro-master.tar.gz
linux-0.01-distro-master.tar.bz2
linux-0.01-distro-master.zip
Added gccHEADmaster
Diffstat (limited to 'gcc-1.40/gcc.aux')
-rw-r--r--gcc-1.40/gcc.aux192
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diff --git a/gcc-1.40/gcc.aux b/gcc-1.40/gcc.aux
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+'xrdef {Copying-pg}{1}
+'xrdef {Copying-snt}{}
+'xrdef {Copying-pg}{1}
+'xrdef {Copying-snt}{}
+'xrdef {Copying-pg}{2}
+'xrdef {Copying-snt}{}
+'xrdef {Copying-pg}{5}
+'xrdef {Copying-snt}{}
+'xrdef {Contributors-pg}{7}
+'xrdef {Contributors-snt}{}
+'xrdef {Boycott-pg}{9}
+'xrdef {Boycott-snt}{chapter'tie1}
+'xrdef {Options-pg}{13}
+'xrdef {Options-snt}{chapter'tie2}
+'xrdef {Installation-pg}{27}
+'xrdef {Installation-snt}{chapter'tie3}
+'xrdef {Other Dir-pg}{34}
+'xrdef {Other Dir-snt}{section'tie3.1}
+'xrdef {Sun Install-pg}{35}
+'xrdef {Sun Install-snt}{section'tie3.2}
+'xrdef {3b1 Install-pg}{36}
+'xrdef {3b1 Install-snt}{section'tie3.3}
+'xrdef {SCO Install-pg}{36}
+'xrdef {SCO Install-snt}{section'tie3.4}
+'xrdef {VMS Install-pg}{37}
+'xrdef {VMS Install-snt}{section'tie3.5}
+'xrdef {HPUX Install-pg}{40}
+'xrdef {HPUX Install-snt}{section'tie3.6}
+'xrdef {Tower Install-pg}{40}
+'xrdef {Tower Install-snt}{section'tie3.7}
+'xrdef {Trouble-pg}{41}
+'xrdef {Trouble-snt}{chapter'tie4}
+'xrdef {Service-pg}{43}
+'xrdef {Service-snt}{chapter'tie5}
+'xrdef {Incompatibilities-pg}{45}
+'xrdef {Incompatibilities-snt}{chapter'tie6}
+'xrdef {Extensions-pg}{49}
+'xrdef {Extensions-snt}{chapter'tie7}
+'xrdef {Statement Exprs-pg}{49}
+'xrdef {Statement Exprs-snt}{section'tie7.1}
+'xrdef {Naming Types-pg}{50}
+'xrdef {Naming Types-snt}{section'tie7.2}
+'xrdef {Typeof-pg}{50}
+'xrdef {Typeof-snt}{section'tie7.3}
+'xrdef {Lvalues-pg}{51}
+'xrdef {Lvalues-snt}{section'tie7.4}
+'xrdef {Conditionals-pg}{52}
+'xrdef {Conditionals-snt}{section'tie7.5}
+'xrdef {Zero-Length-pg}{53}
+'xrdef {Zero-Length-snt}{section'tie7.6}
+'xrdef {Variable-Length-pg}{53}
+'xrdef {Variable-Length-snt}{section'tie7.7}
+'xrdef {Subscripting-pg}{54}
+'xrdef {Subscripting-snt}{section'tie7.8}
+'xrdef {Pointer Arith-pg}{55}
+'xrdef {Pointer Arith-snt}{section'tie7.9}
+'xrdef {Initializers-pg}{55}
+'xrdef {Initializers-snt}{section'tie7.10}
+'xrdef {Constructors-pg}{55}
+'xrdef {Constructors-snt}{section'tie7.11}
+'xrdef {Function Attributes-pg}{56}
+'xrdef {Function Attributes-snt}{section'tie7.12}
+'xrdef {Dollar Signs-pg}{57}
+'xrdef {Dollar Signs-snt}{section'tie7.13}
+'xrdef {Alignment-pg}{57}
+'xrdef {Alignment-snt}{section'tie7.14}
+'xrdef {Inline-pg}{58}
+'xrdef {Inline-snt}{section'tie7.15}
+'xrdef {Extended Asm-pg}{59}
+'xrdef {Extended Asm-snt}{section'tie7.16}
+'xrdef {Asm Labels-pg}{63}
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+'xrdef {Explicit Reg Vars-pg}{64}
+'xrdef {Explicit Reg Vars-snt}{section'tie7.18}
+'xrdef {Global Reg Vars-pg}{64}
+'xrdef {Global Reg Vars-snt}{section'tie7.18.1}
+'xrdef {Local Reg Vars-pg}{66}
+'xrdef {Local Reg Vars-snt}{section'tie7.18.2}
+'xrdef {Alternate Keywords-pg}{66}
+'xrdef {Alternate Keywords-snt}{section'tie7.19}
+'xrdef {Bugs-pg}{69}
+'xrdef {Bugs-snt}{chapter'tie8}
+'xrdef {Bug Criteria-pg}{69}
+'xrdef {Bug Criteria-snt}{section'tie8.1}
+'xrdef {Bug Reporting-pg}{70}
+'xrdef {Bug Reporting-snt}{section'tie8.2}
+'xrdef {Portability-pg}{75}
+'xrdef {Portability-snt}{chapter'tie9}
+'xrdef {Interface-pg}{77}
+'xrdef {Interface-snt}{chapter'tie10}
+'xrdef {Passes-pg}{79}
+'xrdef {Passes-snt}{chapter'tie11}
+'xrdef {RTL-pg}{85}
+'xrdef {RTL-snt}{chapter'tie12}
+'xrdef {RTL Objects-pg}{85}
+'xrdef {RTL Objects-snt}{section'tie12.1}
+'xrdef {Accessors-pg}{86}
+'xrdef {Accessors-snt}{section'tie12.2}
+'xrdef {Flags-pg}{88}
+'xrdef {Flags-snt}{section'tie12.3}
+'xrdef {Machine Modes-pg}{90}
+'xrdef {Machine Modes-snt}{section'tie12.4}
+'xrdef {Constants-pg}{92}
+'xrdef {Constants-snt}{section'tie12.5}
+'xrdef {Regs and Memory-pg}{94}
+'xrdef {Regs and Memory-snt}{section'tie12.6}
+'xrdef {Arithmetic-pg}{96}
+'xrdef {Arithmetic-snt}{section'tie12.7}
+'xrdef {Comparisons-pg}{98}
+'xrdef {Comparisons-snt}{section'tie12.8}
+'xrdef {Bit Fields-pg}{100}
+'xrdef {Bit Fields-snt}{section'tie12.9}
+'xrdef {Conversions-pg}{100}
+'xrdef {Conversions-snt}{section'tie12.10}
+'xrdef {RTL Declarations-pg}{101}
+'xrdef {RTL Declarations-snt}{section'tie12.11}
+'xrdef {Side Effects-pg}{102}
+'xrdef {Side Effects-snt}{section'tie12.12}
+'xrdef {Incdec-pg}{105}
+'xrdef {Incdec-snt}{section'tie12.13}
+'xrdef {Assembler-pg}{106}
+'xrdef {Assembler-snt}{section'tie12.14}
+'xrdef {Insns-pg}{107}
+'xrdef {Insns-snt}{section'tie12.15}
+'xrdef {Calls-pg}{111}
+'xrdef {Calls-snt}{section'tie12.16}
+'xrdef {Sharing-pg}{112}
+'xrdef {Sharing-snt}{section'tie12.17}
+'xrdef {Machine Desc-pg}{115}
+'xrdef {Machine Desc-snt}{chapter'tie13}
+'xrdef {Patterns-pg}{115}
+'xrdef {Patterns-snt}{section'tie13.1}
+'xrdef {Example-pg}{116}
+'xrdef {Example-snt}{section'tie13.2}
+'xrdef {RTL Template-pg}{117}
+'xrdef {RTL Template-snt}{section'tie13.3}
+'xrdef {Output Template-pg}{120}
+'xrdef {Output Template-snt}{section'tie13.4}
+'xrdef {Output Statement-pg}{121}
+'xrdef {Output Statement-snt}{section'tie13.5}
+'xrdef {Constraints-pg}{122}
+'xrdef {Constraints-snt}{section'tie13.6}
+'xrdef {Simple Constraints-pg}{122}
+'xrdef {Simple Constraints-snt}{section'tie13.6.1}
+'xrdef {Multi-Alternative-pg}{126}
+'xrdef {Multi-Alternative-snt}{section'tie13.6.2}
+'xrdef {Class Preferences-pg}{127}
+'xrdef {Class Preferences-snt}{section'tie13.6.3}
+'xrdef {Modifiers-pg}{128}
+'xrdef {Modifiers-snt}{section'tie13.6.4}
+'xrdef {No Constraints-pg}{129}
+'xrdef {No Constraints-snt}{section'tie13.6.5}
+'xrdef {Standard Names-pg}{129}
+'xrdef {Standard Names-snt}{section'tie13.7}
+'xrdef {Pattern Ordering-pg}{135}
+'xrdef {Pattern Ordering-snt}{section'tie13.8}
+'xrdef {Dependent Patterns-pg}{135}
+'xrdef {Dependent Patterns-snt}{section'tie13.9}
+'xrdef {Jump Patterns-pg}{138}
+'xrdef {Jump Patterns-snt}{section'tie13.10}
+'xrdef {Peephole Definitions-pg}{138}
+'xrdef {Peephole Definitions-snt}{section'tie13.11}
+'xrdef {Expander Definitions-pg}{142}
+'xrdef {Expander Definitions-snt}{section'tie13.12}
+'xrdef {Machine Macros-pg}{147}
+'xrdef {Machine Macros-snt}{chapter'tie14}
+'xrdef {Run-time Target-pg}{147}
+'xrdef {Run-time Target-snt}{section'tie14.1}
+'xrdef {Storage Layout-pg}{148}
+'xrdef {Storage Layout-snt}{section'tie14.2}
+'xrdef {Registers-pg}{150}
+'xrdef {Registers-snt}{section'tie14.3}
+'xrdef {Register Classes-pg}{155}
+'xrdef {Register Classes-snt}{section'tie14.4}
+'xrdef {Stack Layout-pg}{159}
+'xrdef {Stack Layout-snt}{section'tie14.5}
+'xrdef {Library Calls-pg}{167}
+'xrdef {Library Calls-snt}{section'tie14.6}
+'xrdef {Addressing Modes-pg}{168}
+'xrdef {Addressing Modes-snt}{section'tie14.7}
+'xrdef {Delayed Branch-pg}{170}
+'xrdef {Delayed Branch-snt}{section'tie14.8}
+'xrdef {Condition Code-pg}{171}
+'xrdef {Condition Code-snt}{section'tie14.9}
+'xrdef {Cross-compilation-pg}{172}
+'xrdef {Cross-compilation-snt}{section'tie14.10}
+'xrdef {Misc-pg}{174}
+'xrdef {Misc-snt}{section'tie14.11}
+'xrdef {Assembler Format-pg}{177}
+'xrdef {Assembler Format-snt}{section'tie14.12}
+'xrdef {Config-pg}{189}
+'xrdef {Config-snt}{chapter'tie15}