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Post r15: Remove hardware.h

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This commit is contained in:
AloXado320 2021-12-01 00:13:18 -05:00
parent d712d95f65
commit 4e49a42dfc
36 changed files with 297 additions and 501 deletions
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32
enhancements/ique_support.patch
View file

@ -40,13 +40,13 @@ index 990cb11f..22756e91 100644
--- a/lib/src/__osViSwapContext.c
+++ b/lib/src/__osViSwapContext.c
@@ -54,7 +54,9 @@ void __osViSwapContext() {
HW_REG(VI_INTR_REG, u32) = s0->fldRegs[field].vIntr;
HW_REG(VI_X_SCALE_REG, u32) = s1->unk20;
HW_REG(VI_Y_SCALE_REG, u32) = s1->unk2c;
- HW_REG(VI_CONTROL_REG, u32) = s1->features;
IO_WRITE(VI_INTR_REG, s0->fldRegs[field].vIntr);
IO_WRITE(VI_X_SCALE_REG, s1->unk20);
IO_WRITE(VI_Y_SCALE_REG, s1->unk2c);
- IO_WRITE(VI_CONTROL_REG, s1->features);
+ /* Make sure bit 13 is cleared. Otherwise, graphics will be corrupted on
+ * iQue Player. This has no effect on N64. */
+ HW_REG(VI_CONTROL_REG, u32) = s1->features & ~(1 << 13);
+ IO_WRITE(VI_CONTROL_REG, s1->features & ~(1 << 13));
__osViNext = __osViCurr;
__osViCurr = s1;
*__osViNext = *__osViCurr;
@ -272,22 +272,24 @@ diff --git a/lib/src/osInitialize.c b/lib/src/osInitialize.c
index ba73024b..6deaf407 100644
--- a/lib/src/osInitialize.c
+++ b/lib/src/osInitialize.c
@@ -1,6 +1,7 @@
#include "libultra_internal.h"
#include "hardware.h"
@@ -3,6 +3,7 @@
#include "piint.h"
#include "PR/rcp.h"
#include <macros.h>
+#include <PR/console_type.h>
#define PIF_ADDR_START (void *) 0x1FC007FC
@@ -51,6 +52,7 @@ void osInitialize(void) {
UNUSED u32 eu_sp30;
typedef struct {
@@ -45,8 +45,9 @@ void osInitialize(void) {
u32 status;
#endif
UNUSED u32 sp2c;
+ gConsoleType = get_console_type();
D_80365CD0 = TRUE;
__osSetSR(__osGetSR() | 0x20000000);
__osSetFpcCsr(0x01000800);
__osFinalrom = TRUE;
__osSetSR(__osGetSR() | SR_CU1);
__osSetFpcCsr(FPCSR_FS | FPCSR_EV);
diff --git a/sm64.ld b/sm64.ld
index da9bc4dd..9c1cebba 100755
--- a/sm64.ld

22
include/PR/os_vi.h
View file

@ -4,6 +4,16 @@
#include <PR/ultratypes.h>
#include <PR/os_message.h>
//TODO: figure out what this is
#define VI_STATE_01 0x01
#define VI_STATE_XSCALE_UPDATED 0x02
#define VI_STATE_YSCALE_UPDATED 0x04
#define VI_STATE_08 0x08 //related to control regs changing
#define VI_STATE_10 0x10 //swap buffer
#define VI_STATE_BLACK 0x20 //probably related to a black screen
#define VI_STATE_REPEATLINE 0x40 //repeat line?
#define VI_STATE_FADE 0x80 //fade
/* Ultra64 Video Interface */
@ -27,8 +37,7 @@
/* Types */
typedef struct
{
typedef struct {
u32 ctrl;
u32 width;
u32 burst;
@ -40,8 +49,7 @@ typedef struct
u32 vCurrent;
} OSViCommonRegs;
typedef struct
{
typedef struct {
u32 origin;
u32 yScale;
u32 vStart;
@ -49,15 +57,13 @@ typedef struct
u32 vIntr;
} OSViFieldRegs;
typedef struct
{
typedef struct {
u8 type;
OSViCommonRegs comRegs;
OSViFieldRegs fldRegs[2];
} OSViMode;
typedef struct
{
typedef struct {
/* 0x00 */ u16 unk00; //some kind of flags. swap buffer sets to 0x10
/* 0x02 */ u16 retraceCount;
/* 0x04 */ void* buffer;

51
lib/src/D_802F4380.c
View file

@ -1,10 +1,11 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "piint.h"
#include "PR/rcp.h"
#include "new_func.h"
#include "macros.h"
#if defined(VERSION_EU)
u32 D_802F4380() {
s32 __osLeoInterrupt(void) {
u32 sp3c;
u32 sp38;
u32 sp34;
@ -12,45 +13,45 @@ u32 D_802F4380() {
__OSBlockInfo *sp2c;
u32 sp28;
UNUSED __OSBlockInfo *sp24;
if (!EU_D_80302090) {
if (!osDDActive) {
return 0;
}
sp30 = &__osDiskHandle->transferInfo;
sp2c = &sp30->block[sp30->blockNum];
sp38 = HW_REG(PI_STATUS_REG, u32);
if (sp38 & PI_STATUS_BUSY) {
HW_REG(PI_STATUS_REG, u32) = PI_STATUS_RESET_CONTROLLER | PI_STATUS_CLEAR_INTR;
WAIT_ON_IOBUSY(sp38);
sp3c = HW_REG(ASIC_STATUS, u32);
if (sp3c & MECHANIC_INTERRUPT) {
WAIT_ON_IOBUSY(sp38);
HW_REG(ASIC_BM_CTL, u32) = sp30->bmCtlShadow | MECHANIC_INTERRUPT_RESET;
sp38 = IO_READ(PI_STATUS_REG);
if (sp38 & PI_STATUS_DMA_BUSY) {
IO_WRITE(PI_STATUS_REG, PI_STATUS_RESET | PI_STATUS_CLR_INTR);
WAIT_ON_LEO_IO_BUSY(sp38);
sp3c = IO_READ(LEO_STATUS);
if (sp3c & LEO_STATUS_MECHANIC_INTERRUPT) {
WAIT_ON_LEO_IO_BUSY(sp38);
IO_WRITE(LEO_BM_CTL, sp30->bmCtlShadow | LEO_BM_CTL_CLR_MECHANIC_INTR);
}
sp30->errStatus = 75;
func_802F4A20();
return 1;
}
WAIT_ON_IOBUSY(sp38);
sp3c = HW_REG(ASIC_STATUS, u32);
if (sp3c & MECHANIC_INTERRUPT) {
WAIT_ON_IOBUSY(sp38);
HW_REG(ASIC_BM_CTL, u32) = sp30->bmCtlShadow | MECHANIC_INTERRUPT_RESET;
WAIT_ON_LEO_IO_BUSY(sp38);
sp3c = IO_READ(LEO_STATUS);
if (sp3c & LEO_STATUS_MECHANIC_INTERRUPT) {
WAIT_ON_LEO_IO_BUSY(sp38);
IO_WRITE(LEO_BM_CTL, sp30->bmCtlShadow | LEO_BM_CTL_CLR_MECHANIC_INTR);
sp30->errStatus = 0;
return 0;
}
if (sp3c & BUFFER_MANAGER_ERROR) {
if (sp3c & LEO_STATUS_BUFFER_MANAGER_ERROR) {
sp30->errStatus = 3;
func_802F4A20();
return 1;
}
if (sp30->cmdType == 1) {
if ((sp3c & DATA_REQUEST) == 0) {
if ((sp3c & LEO_STATUS_DATA_REQUEST) == 0) {
if (sp30->sectorNum + 1 != sp30->transferMode * 85) {
sp30->errStatus = 6;
func_802F4A20();
return 1;
}
HW_REG(PI_STATUS_REG, u32) = PI_STATUS_CLEAR_INTR;
IO_WRITE(PI_STATUS_REG, PI_STATUS_CLR_INTR);
__OSGlobalIntMask |= 0x00100401;
sp30->errStatus = 0;
func_802F4B08();
@ -68,7 +69,7 @@ u32 D_802F4380() {
func_802F4A20();
return 1;
}
if ((sp3c & DATA_REQUEST) == 0) {
if ((sp3c & LEO_STATUS_DATA_REQUEST) == 0) {
sp30->errStatus = 17;
func_802F4A20();
return 1;
@ -76,8 +77,8 @@ u32 D_802F4380() {
} else {
sp2c->dramAddr = (void *) ((u32) sp2c->dramAddr + sp2c->sectorSize);
}
sp34 = HW_REG(ASIC_BM_STATUS, u32);
if (((C1_SINGLE & sp34) && (C1_DOUBLE & sp34)) || (sp34 & MICRO_STATUS)) {
sp34 = IO_READ(LEO_BM_STATUS);
if (((LEO_BM_STATUS_C1SINGLE & sp34) && (LEO_BM_STATUS_C1DOUBLE & sp34)) || (sp34 & LEO_BM_STATUS_MICRO)) {
if (sp2c->C1ErrNum > 3) {
if (sp30->transferMode != 3 || sp30->sectorNum > 0x52) {
sp30->errStatus = 17;
@ -90,7 +91,7 @@ u32 D_802F4380() {
}
sp2c->C1ErrNum++;
}
if (sp3c & C2_TRANSFER) {
if (sp3c & LEO_STATUS_C2_TRANSFER) {
if (sp30->sectorNum != 87) {
sp30->errStatus = 6;
func_802F4A20();
@ -101,7 +102,7 @@ u32 D_802F4380() {
sp30->block[1].dramAddr =
(void *) ((u32) sp30->block[1].dramAddr - sp30->block[1].sectorSize);
} else {
HW_REG(PI_STATUS_REG, u32) = PI_STATUS_CLEAR_INTR;
IO_WRITE(PI_STATUS_REG, PI_STATUS_CLR_INTR);
__OSGlobalIntMask |= 0x00100401;
}
osEPiRawStartDma(__osDiskHandle, 0, 0x5000000, sp2c->C2Addr, sp2c->sectorSize * 4);
@ -123,7 +124,7 @@ u32 D_802F4380() {
func_802F4B08();
}
sp30->sectorNum++;
if (sp3c & DATA_REQUEST) {
if (sp3c & LEO_STATUS_DATA_REQUEST) {
if (sp30->sectorNum > 0x54) {
sp30->errStatus = 6;
func_802F4A20();

6
lib/src/__osAiDeviceBusy.c
View file

@ -1,9 +1,9 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
s32 __osAiDeviceBusy(void) {
register s32 status = HW_REG(AI_STATUS_REG, u32);
if ((status & AI_STATUS_AI_FULL) != 0) {
register s32 status = IO_READ(AI_STATUS_REG);
if (status & AI_STATUS_FIFO_FULL) {
return 1;
} else {
return 0;

3
lib/src/__osDevMgrMain.c
View file

@ -3,6 +3,7 @@
#if defined(VERSION_EU) || defined(VERSION_SH)
#include "new_func.h"
#include "PR/rcp.h"
void __osDevMgrMain(void *args) {
OSIoMesg *mb;
@ -58,7 +59,7 @@ void __osDevMgrMain(void *args) {
__osEPiRawWriteIo(mb->piHandle, 0x5000510, sp24->bmCtlShadow | 0x1000000);
}
sp28->errStatus = 4;
HW_REG(PI_STATUS_REG, u32) = PI_STATUS_CLEAR_INTR;
IO_WRITE(PI_STATUS_REG, PI_STATUS_CLR_INTR);
__osSetGlobalIntMask(0x100C01);
}
osSendMesg(mb->hdr.retQueue, mb, OS_MESG_NOBLOCK);

13
lib/src/__osEPiRawReadIo.c
View file

@ -1,11 +1,12 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
#include "piint.h"
s32 __osEPiRawReadIo(OSPiHandle *arg0, u32 devAddr, u32 *data) {
s32 __osEPiRawReadIo(OSPiHandle *pihandle, u32 devAddr, u32 *data) {
register s32 stat;
while (stat = HW_REG(PI_STATUS_REG, s32), stat & (PI_STATUS_BUSY | PI_STATUS_IOBUSY | PI_STATUS_ERROR)) {
;
}
*data = HW_REG(arg0->baseAddress | devAddr, s32);
WAIT_ON_IO_BUSY(stat);
*data = IO_READ(pihandle->baseAddress | devAddr);
return 0;
}

39
lib/src/__osEPiRawWriteIo.c
View file

@ -1,35 +1,12 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
#include "piint.h"
s32 __osEPiRawWriteIo(OSPiHandle *pihandle, u32 devAddr, u32 data) {
register u32 stat;
WAIT_ON_IO_BUSY(stat);
IO_WRITE(pihandle->baseAddress | devAddr, data);
s32 __osEPiRawWriteIo(OSPiHandle *a0, u32 a1, u32 a2) {
register u32 a3 = HW_REG(PI_STATUS_REG, u32);
while (a3 & PI_STATUS_ERROR)
a3 = HW_REG(PI_STATUS_REG, u32);
HW_REG(a0->baseAddress | a1, u32) = a2;
return 0;
}
/*
/ 0B69A0 802F71A0 3C0EA460 / lui $t6, %hi(PI_STATUS_REG) # $t6, 0xa460
/ 0B69A4 802F71A4 8DC70010 / lw $a3, %lo(PI_STATUS_REG)($t6)
/ 0B69A8 802F71A8 27BDFFF8 / addiu $sp, $sp, -8
/ 0B69AC 802F71AC 30EF0003 / andi $t7, $a3, 3
/ 0B69B0 802F71B0 11E00006 / beqz $t7, .L802F71CC
/ 0B69B4 802F71B4 00000000 / nop
.L802F71B8:
/ 0B69B8 802F71B8 3C18A460 / lui $t8, %hi(PI_STATUS_REG) # $t8, 0xa460
/ 0B69BC 802F71BC 8F070010 / lw $a3, %lo(PI_STATUS_REG)($t8)
/ 0B69C0 802F71C0 30F90003 / andi $t9, $a3, 3
/ 0B69C4 802F71C4 1720FFFC / bnez $t9, .L802F71B8
/ 0B69C8 802F71C8 00000000 / nop
.L802F71CC:
/ 0B69CC 802F71CC 8C88000C / lw $t0, 0xc($a0)
/ 0B69D0 802F71D0 3C01A000 / lui $at, 0xa000
/ 0B69D4 802F71D4 27BD0008 / addiu $sp, $sp, 8
/ 0B69D8 802F71D8 01054825 / or $t1, $t0, $a1
/ 0B69DC 802F71DC 01215025 / or $t2, $t1, $at
/ 0B69E0 802F71E0 AD460000 / sw $a2, ($t2)
/ 0B69E4 802F71E4 03E00008 / jr $ra
/ 0B69E8 802F71E8 00001025 / move $v0, $zero
/ 0B69EC 802F71EC 00000000 / nop */

11
lib/src/__osSetGlobalIntMask.c
View file

@ -1,9 +1,8 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "new_func.h"
#include "PR/os.h"
void __osSetGlobalIntMask(s32 arg0) {
register u32 prev = __osDisableInt();
__OSGlobalIntMask |= arg0;
__osRestoreInt(prev);
void __osSetGlobalIntMask(s32 mask) {
register u32 saveMask = __osDisableInt();
__OSGlobalIntMask |= mask;
__osRestoreInt(saveMask);
}

6
lib/src/__osSiDeviceBusy.c
View file

@ -1,10 +1,10 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
s32 __osSiDeviceBusy() {
register u32 status;
status = HW_REG(SI_STATUS_REG, u32);
if (status & (SI_STATUS_DMA_BUSY | SI_STATUS_IO_READ_BUSY)) {
status = IO_READ(SI_STATUS_REG);
if (status & (SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY)) {
return 1;
} else {
return 0;

6
lib/src/__osSiRawReadIo.c
View file

@ -1,10 +1,10 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
s32 __osSiRawReadIo(void *a0, u32 *a1) {
s32 __osSiRawReadIo(u32 devAddr, u32 *data) {
if (__osSiDeviceBusy()) {
return -1;
}
*a1 = HW_REG((uintptr_t) a0, u32);
*data = IO_READ(devAddr);
return 0;
}

8
lib/src/__osSiRawStartDma.c
View file

@ -1,5 +1,5 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
s32 __osSiRawStartDma(s32 dir, void *addr) {
if (__osSiDeviceBusy()) {
@ -10,12 +10,12 @@ s32 __osSiRawStartDma(s32 dir, void *addr) {
osWritebackDCache(addr, 64);
}
HW_REG(SI_DRAM_ADDR_REG, void *) = (void *) osVirtualToPhysical(addr);
IO_WRITE(SI_DRAM_ADDR_REG, osVirtualToPhysical(addr));
if (dir == OS_READ) {
HW_REG(SI_PIF_ADDR_RD64B_REG, u32) = 0x1FC007C0;
IO_WRITE(SI_PIF_ADDR_RD64B_REG, 0x1FC007C0);
} else {
HW_REG(SI_PIF_ADDR_WR64B_REG, u32) = 0x1FC007C0;
IO_WRITE(SI_PIF_ADDR_WR64B_REG, 0x1FC007C0);
}
if (dir == OS_READ) {

6
lib/src/__osSiRawWriteIo.c
View file

@ -1,10 +1,10 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
s32 __osSiRawWriteIo(void *a0, u32 a1) {
s32 __osSiRawWriteIo(u32 devAddr, u32 data) {
if (__osSiDeviceBusy()) {
return -1;
}
HW_REG((uintptr_t) a0, u32) = a1;
IO_WRITE(devAddr, data);
return 0;
}

6
lib/src/__osSpDeviceBusy.c
View file

@ -1,10 +1,12 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
s32 __osSpDeviceBusy() {
register u32 status = HW_REG(SP_STATUS_REG, u32);
register u32 status = IO_READ(SP_STATUS_REG);
if (status & (SPSTATUS_IO_FULL | SPSTATUS_DMA_FULL | SPSTATUS_DMA_BUSY)) {
return 1;
}
return 0;
}

4
lib/src/__osSpGetStatus.c
View file

@ -1,6 +1,6 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
u32 __osSpGetStatus() {
return HW_REG(SP_STATUS_REG, u32);
return IO_READ(SP_STATUS_REG);
}

10
lib/src/__osSpRawStartDma.c
View file

@ -1,16 +1,16 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
s32 __osSpRawStartDma(u32 dir, void *sp_ptr, void *dram_ptr, size_t size) {
if (__osSpDeviceBusy()) {
return -1;
}
HW_REG(SP_MEM_ADDR_REG, void *) = sp_ptr;
HW_REG(SP_DRAM_ADDR_REG, void *) = (void *) osVirtualToPhysical(dram_ptr);
IO_WRITE(SP_MEM_ADDR_REG, sp_ptr);
IO_WRITE(SP_DRAM_ADDR_REG, osVirtualToPhysical(dram_ptr));
if (dir == 0) {
HW_REG(SP_WR_LEN_REG, u32) = size - 1;
IO_WRITE(SP_WR_LEN_REG, size - 1);
} else {
HW_REG(SP_RD_LEN_REG, u32) = size - 1;
IO_WRITE(SP_RD_LEN_REG, size - 1);
}
return 0;
}

6
lib/src/__osSpSetPc.c
View file

@ -1,12 +1,12 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
s32 __osSpSetPc(void *pc) {
register u32 status = HW_REG(SP_STATUS_REG, u32);
register u32 status = IO_READ(SP_STATUS_REG);
if (!(status & SPSTATUS_HALT)) {
return -1;
} else {
HW_REG(SP_PC_REG, void *) = pc;
IO_WRITE(SP_PC_REG, pc);
return 0;
}
}

4
lib/src/__osSpSetStatus.c
View file

@ -1,6 +1,6 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
void __osSpSetStatus(u32 status) {
HW_REG(SP_STATUS_REG, u32) = status;
IO_WRITE(SP_STATUS_REG, status);
}

66
lib/src/__osViInit.c
View file

@ -1,15 +1,17 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
#include "PR/os.h"
OSViContext sViContexts[2] = { 0 };
OSViContext *__osViCurr = &sViContexts[0];
OSViContext *__osViNext = &sViContexts[1];
#ifdef VERSION_EU
u32 osViClock = 0x02E6D354; // used for audio frequency calculations
u32 osViClock = VI_NTSC_CLOCK;
u32 sTvType = TV_TYPE_PAL;
#elif !defined(VERSION_SH)
u32 sTvType = TV_TYPE_NTSC;
u32 osViClock = 0x02E6D354;
u32 osViClock = VI_NTSC_CLOCK;
#endif
extern OSViMode osViModePalLan1;
@ -19,31 +21,44 @@ extern OSViMode osViModeNtscLan1;
#endif
void __osViInit(void) {
//#ifdef VERSION_JP
#ifdef VERSION_US
sTvType = osTvType;
#endif
bzero(sViContexts, sizeof(sViContexts));
__osViCurr = &sViContexts[0];
__osViNext = &sViContexts[1];
__osViNext->retraceCount = 1;
__osViCurr->retraceCount = 1;
#if defined(VERSION_EU)
#if defined(VERSION_JP)
if (sTvType != TV_TYPE_PAL) {
__osViNext->modep = &osViModePalLan1;
osViClock = VI_NTSC_CLOCK;
} else {
__osViNext->modep = &osViModeMpalLan1;
osViClock = VI_PAL_CLOCK;
}
#elif defined(VERSION_US)
if (sTvType == TV_TYPE_NTSC) {
__osViNext->modep = &osViModePalLan1;
osViClock = VI_NTSC_CLOCK;
} else {
__osViNext->modep = &osViModeMpalLan1;
osViClock = VI_MPAL_CLOCK;
}
#elif defined(VERSION_EU)
if (osTvType == TV_TYPE_PAL) {
__osViNext->modep = &osViModePalLan1;
osViClock = 0x02F5B2D2;
osViClock = VI_PAL_CLOCK;
} else if (osTvType == TV_TYPE_MPAL) {
__osViNext->modep = &osViModeMpalLan1;
osViClock = 0x02E6025C;
osViClock = VI_MPAL_CLOCK;
} else {
__osViNext->modep = &osViModeNtscLan1;
osViClock = 0x02E6D354;
osViClock = VI_NTSC_CLOCK;
}
#elif defined(VERSION_SH)
#else
__osViNext->buffer = (void *) 0x80000000;
__osViCurr->buffer = (void *) 0x80000000;
if (osTvType == TV_TYPE_PAL) {
@ -53,35 +68,16 @@ void __osViInit(void) {
} else {
__osViNext->modep = &osViModeNtscLan1;
}
#else
#ifdef VERSION_JP
if (sTvType != TV_TYPE_PAL)
#else
if (sTvType == TV_TYPE_NTSC)
#endif
{
__osViNext->modep = &osViModePalLan1;
osViClock = 0x02E6D354;
} else {
__osViNext->modep = &osViModeMpalLan1;
#if defined(VERSION_JP)
osViClock = 0x02F5B2D2;
#elif defined(VERSION_US)
osViClock = 0x02E6025C;
#endif
}
#endif
__osViNext->unk00 = 0x20;
__osViNext->unk00 = VI_STATE_BLACK;
__osViNext->features = __osViNext->modep->comRegs.ctrl;
#ifndef VERSION_JP
while (HW_REG(VI_CURRENT_REG, u32) > 0xa) {
while (IO_READ(VI_CURRENT_REG) > 10) {
;
}
HW_REG(VI_STATUS_REG, u32) = 0;
IO_WRITE(VI_STATUS_REG, 0);
#endif
__osViSwapContext();
}

30
lib/src/__osViSwapContext.c
View file

@ -1,5 +1,5 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
extern OSViContext *__osViNext;
extern OSViContext *__osViCurr;
@ -15,7 +15,7 @@ void __osViSwapContext() {
field = 0;
s1 = __osViNext;
s0 = s1->modep;
field = HW_REG(VI_V_CURRENT_LINE_REG, u32) & 1;
field = IO_READ(VI_V_CURRENT_LINE_REG) & 1;
s2 = osVirtualToPhysical(s1->buffer);
origin = (s0->fldRegs[field].origin) + s2;
if (s1->unk00 & 2) {
@ -42,19 +42,19 @@ void __osViSwapContext() {
s1->unk2c = (s1->unk28 << 0x10) & 0x3ff0000;
origin = osVirtualToPhysical(s1->buffer);
}
HW_REG(VI_ORIGIN_REG, u32) = origin;
HW_REG(VI_WIDTH_REG, u32) = s0->comRegs.width;
HW_REG(VI_BURST_REG, u32) = s0->comRegs.burst;
HW_REG(VI_V_SYNC_REG, u32) = s0->comRegs.vSync;
HW_REG(VI_H_SYNC_REG, u32) = s0->comRegs.hSync;
HW_REG(VI_LEAP_REG, u32) = s0->comRegs.leap;
HW_REG(VI_H_START_REG, u32) = hStart;
HW_REG(VI_V_START_REG, u32) = s0->fldRegs[field].vStart;
HW_REG(VI_V_BURST_REG, u32) = s0->fldRegs[field].vBurst;
HW_REG(VI_INTR_REG, u32) = s0->fldRegs[field].vIntr;
HW_REG(VI_X_SCALE_REG, u32) = s1->unk20;
HW_REG(VI_Y_SCALE_REG, u32) = s1->unk2c;
HW_REG(VI_CONTROL_REG, u32) = s1->features;
IO_WRITE(VI_ORIGIN_REG, origin);
IO_WRITE(VI_WIDTH_REG, s0->comRegs.width);
IO_WRITE(VI_BURST_REG, s0->comRegs.burst);
IO_WRITE(VI_V_SYNC_REG, s0->comRegs.vSync);
IO_WRITE(VI_H_SYNC_REG, s0->comRegs.hSync);
IO_WRITE(VI_LEAP_REG, s0->comRegs.leap);
IO_WRITE(VI_H_START_REG, hStart);
IO_WRITE(VI_V_START_REG, s0->fldRegs[field].vStart);
IO_WRITE(VI_V_BURST_REG, s0->fldRegs[field].vBurst);
IO_WRITE(VI_INTR_REG, s0->fldRegs[field].vIntr);
IO_WRITE(VI_X_SCALE_REG, s1->unk20);
IO_WRITE(VI_Y_SCALE_REG, s1->unk2c);
IO_WRITE(VI_CONTROL_REG, s1->features);
__osViNext = __osViCurr;
__osViCurr = s1;
*__osViNext = *__osViCurr;

12
lib/src/func_802F4A20.c
View file

@ -1,15 +1,17 @@
#include "PR/rcp.h"
#include "piint.h"
#include "new_func.h"
void func_802F4A20(void) {
__OSTranxInfo *sp1c;
volatile u32 sp18;
sp1c = &__osDiskHandle->transferInfo;
WAIT_ON_IOBUSY(sp18);
HW_REG(ASIC_BM_CTL, u32) = BUFFER_MANAGER_RESET | sp1c->bmCtlShadow; //should be unk10??
WAIT_ON_IOBUSY(sp18);
HW_REG(ASIC_BM_CTL, u32) = sp1c->bmCtlShadow;
WAIT_ON_LEO_IO_BUSY(sp18);
IO_WRITE(LEO_BM_CTL, (LEO_BM_CTL_RESET | sp1c->bmCtlShadow));
WAIT_ON_LEO_IO_BUSY(sp18);
IO_WRITE(LEO_BM_CTL, sp1c->bmCtlShadow);
func_802F4B08();
HW_REG(PI_STATUS_REG, u32) = PI_STATUS_CLEAR_INTR;
IO_WRITE(PI_STATUS_REG, PI_STATUS_CLR_INTR);
__OSGlobalIntMask |= 0x00100401; // TODO: fix magic numbers
}

127
lib/src/hardware.h
View file

@ -1,127 +0,0 @@
#ifndef _HARDWARE_H_
#define _HARDWARE_H_
#define HW_REG(reg, type) *(volatile type *)(uintptr_t)((reg) | 0xa0000000)
#define AI_DRAM_ADDR_REG 0x04500000
#define AI_LEN_REG 0x04500004
#define AI_CONTROL_REG 0x04500008
#define AI_STATUS_REG 0x0450000C
#define AI_STATUS_AI_FULL (1 << 31)
#define AI_STATUS_AI_BUSY (1 << 30)
#define AI_DACRATE_REG 0x04500010
#define AI_BITRATE_REG 0x04500014
#define VI_STATUS_REG 0x04400000
#define VI_CONTROL_REG 0x04400000
#define VI_ORIGIN_REG 0x04400004
#define VI_DRAM_ADDR_REG 0x04400004
#define VI_WIDTH_REG 0x04400008
#define VI_H_WIDTH_REG 0x04400008
#define VI_INTR_REG 0x0440000C
#define VI_V_INTER_REG 0x0440000C
#define VI_CURRENT_REG 0x04400010
#define VI_V_CURRENT_LINE_REG 0x04400010
#define VI_BURST_REG 0x04400014
#define VI_TIMING_REG 0x04400014
#define VI_V_SYNC_REG 0x04400018 //VI vertical sync
#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync
#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap
#define VI_H_SYNC_LEAP_REG 0x04400020
#define VI_H_START_REG 0x04400024 //VI horizontal video
#define VI_H_VIDEO_REG 0x04400024
#define VI_V_START_REG 0x04400028 //VI vertical video
#define VI_V_VIDEO_REG 0x04400028
#define VI_V_BURST_REG 0x0440002C //VI vertical burst
#define VI_X_SCALE_REG 0x04400030 //VI x-scale
#define VI_Y_SCALE_REG 0x04400034 //VI y-scale
#define SP_IMEM_START 0x04001000
#define SP_DMEM_START 0x04000000
#define SP_MEM_ADDR_REG 0x04040000
#define SP_DRAM_ADDR_REG 0x04040004
#define SP_RD_LEN_REG 0x04040008
#define SP_WR_LEN_REG 0x0404000C
#define SP_STATUS_REG 0x04040010
#define SP_PC_REG 0x04080000
#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address
#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address
#define PI_RD_LEN_REG 0x04600008 //PI read length
#define PI_WR_LEN_REG 0x0460000C //PI write length
#define PI_STATUS_REG 0x04600010 //PI status
#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency
#define PI_DOMAIN1_REG 0x04600014
#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width
#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size
#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release
#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency
#define PI_DOMAIN2_REG 0x04600024
#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width
#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
#define PI_STATUS_BUSY 0x1
#define PI_STATUS_IOBUSY 0x2
#define PI_STATUS_ERROR 0x3
#define PI_STATUS_RESET_CONTROLLER 0x1
#define PI_STATUS_CLEAR_INTR 0x2
#define SI_DRAM_ADDR_REG 0x04800000
#define SI_PIF_ADDR_RD64B_REG 0x04800004
#define SI_PIF_ADDR_WR64B_REG 0x04800010
#define SI_STATUS_REG 0x04800018
#define SI_STATUS_DMA_BUSY 0x1
#define SI_STATUS_IO_READ_BUSY 0x2
#define SI_STATUS_DMA_ERROR 0x8
#define SI_STATUS_INTERRUPT (1 << 12)
#define MI_INIT_MODE_REG 0x04300000
#define MI_MODE_REG MI_INIT_MODE_REG
#define MI_VERSION_REG 0x04300004
#define MI_INTR_REG 0x04300008
#define MI_INTR_MASK_REG 0x0430000C
//https://github.com/LuigiBlood/64dd/wiki/Registers
#define ASIC_STATUS 0x05000508
#define DATA_REQUEST 0x40000000
#define C2_TRANSFER 0x10000000
#define BUFFER_MANAGER_ERROR 0x08000000
#define BUFFER_MANAGER_INTERRUPT 0x04000000
#define MECHANIC_INTERRUPT 0x02000000
#define DISK_PRESENT 0x01000000
#define BUSY_STATE 0x00800000
#define RESET_STATE 0x00400000
#define MOTOR_NOT_SPINNING 0x00100000
#define HEAD_RETRACTED 0x00080000
#define WRITE_PROTECT_ERROR 0x00040000
#define MECHANIC_ERROR 0x00020000
#define DISK_CHANGE 0x00010000
#define _64DD_PRESENT_MASK 0xFFFF
//ro
#define ASIC_BM_STATUS 0x05000510
#define MICRO_STATUS 0x02000000
#define C1_DOUBLE 0x00400000
#define C1_SINGLE 0x00200000
//wo
#define ASIC_BM_CTL 0x05000510
#define BUFFER_MANAGER_RESET 0x10000000
#define MECHANIC_INTERRUPT_RESET 0x01000000
/*- Start Buffer Manager (0x80000000)
- Buffer Manager Mode (0x40000000)
- BM Interrupt Mask (0x20000000)
- Buffer Manager Reset (0x10000000)
- Disable OR Check? (0x08000000)
- Disable C1 Correction (0x04000000)
- Block Transfer (0x02000000)
- Mechanic Interrupt Reset (0x01000000)*/
#endif

10
lib/src/leointerrupt.c
View file

@ -28,10 +28,10 @@ s32 __osLeoInterrupt() {
__osLeoResume();
return 1;
}
WAIT_ON_IOBUSY(pi_stat);
WAIT_ON_LEO_IO_BUSY(pi_stat);
stat = IO_READ(LEO_STATUS);
if (stat & LEO_STATUS_MECHANIC_INTERRUPT) {
WAIT_ON_IOBUSY(pi_stat);
WAIT_ON_LEO_IO_BUSY(pi_stat);
IO_WRITE(LEO_BM_CTL, info->bmCtlShadow | LEO_BM_CTL_CLR_MECHANIC_INTR);
blockInfo->errStatus = LEO_ERROR_GOOD;
return 0;
@ -40,7 +40,7 @@ s32 __osLeoInterrupt() {
return 1;
}
if (stat & LEO_STATUS_BUFFER_MANAGER_ERROR) {
WAIT_ON_IOBUSY(pi_stat);
WAIT_ON_LEO_IO_BUSY(pi_stat);
stat = IO_READ(LEO_STATUS);
blockInfo->errStatus = LEO_ERROR_22;
__osLeoResume();
@ -155,9 +155,9 @@ static void __osLeoAbnormalResume(void) {
__OSTranxInfo *info;
u32 pi_stat;
info = &__osDiskHandle->transferInfo;
WAIT_ON_IOBUSY(pi_stat);
WAIT_ON_LEO_IO_BUSY(pi_stat);
IO_WRITE(LEO_BM_CTL, info->bmCtlShadow | LEO_BM_CTL_RESET);
WAIT_ON_IOBUSY(pi_stat);
WAIT_ON_LEO_IO_BUSY(pi_stat);
IO_WRITE(LEO_BM_CTL, info->bmCtlShadow);
__osLeoResume();
IO_WRITE(PI_STATUS_REG, PI_STATUS_CLR_INTR);

7
lib/src/libultra_internal.h
View file

@ -76,9 +76,9 @@ void __osPiGetAccess(void);
void __osSetSR(u32);
u32 __osGetSR(void);
void __osSetFpcCsr(u32);
s32 __osSiRawReadIo(void *, u32 *);
s32 __osSiRawWriteIo(void *, u32);
s32 osPiRawReadIo(u32 a0, u32 *a1);
s32 __osSiRawReadIo(u32, u32 *);
s32 __osSiRawWriteIo(u32, u32);
s32 osPiRawReadIo(u32, u32 *);
void __osSpSetStatus(u32);
u32 __osSpGetStatus(void);
s32 __osSpSetPc(void *);
@ -96,4 +96,5 @@ s32 __osAiDeviceBusy(void);
void __osDispatchThread(void);
u32 __osGetCause(void);
s32 __osAtomicDec(u32 *);
void __osSetHWIntrRoutine(OSHWIntr interrupt, s32 (*handler)(void));
#endif

10
lib/src/new_func.h
View file

@ -2,18 +2,12 @@
#define NEW_FUNC_H
#include "libultra_internal.h"
#include "hardware.h"
#define WAIT_ON_IOBUSY(var) \
var = HW_REG(PI_STATUS_REG, u32); \
while (var & PI_STATUS_IOBUSY) \
var = HW_REG(PI_STATUS_REG, u32);
extern u32 EU_D_80302090;
extern u32 osDDActive;
extern OSPiHandle *__osDiskHandle; //possibly __osPiTable
extern volatile u32 __OSGlobalIntMask;
extern /*volatile*/ u32 __OSGlobalIntMask;
s32 osEPiRawStartDma(OSPiHandle *arg0, s32 dir, u32 cart_addr, void *dram_addr, u32 size);
void func_802F4B08(void);
void func_802F4A20(void);

5
lib/src/osAiGetLength.c
View file

@ -1,7 +1,6 @@
#include "libultra_internal.h"
#include "osAi.h"
#include "hardware.h"
#include "PR/rcp.h"
u32 osAiGetLength() {
return HW_REG(AI_LEN_REG, u32);
return IO_READ(AI_LEN_REG);
}

29
lib/src/osAiSetFrequency.c
View file

@ -1,35 +1,32 @@
#include "libultra_internal.h"
#include "osAi.h"
#include "hardware.h"
#include "PR/rcp.h"
#include "osint.h"
#include "macros.h"
extern s32 osViClock;
s32 osAiSetFrequency(u32 freq) {
register u32 a1;
register s32 a2;
register u32 dacRate;
register s32 bitRate;
register float ftmp;
ftmp = osViClock / (float) freq + .5f;
a1 = ftmp;
dacRate = ftmp;
if (a1 < 0x84) {
if (dacRate < AI_MIN_DAC_RATE) {
return -1;
}
a2 = (a1 / 66) & 0xff;
if (a2 > 16) {
a2 = 16;
bitRate = (dacRate / 66) & 0xff;
if (bitRate > AI_MAX_BIT_RATE) {
bitRate = AI_MAX_BIT_RATE;
}
HW_REG(AI_DACRATE_REG, u32) = a1 - 1;
HW_REG(AI_BITRATE_REG, u32) = a2 - 1;
HW_REG(AI_CONTROL_REG, u32) = 1; // enable dma
return osViClock / (s32) a1;
IO_WRITE(AI_DACRATE_REG, dacRate - 1);
IO_WRITE(AI_BITRATE_REG, bitRate - 1);
IO_WRITE(AI_CONTROL_REG, AI_CONTROL_DMA_ON);
return osViClock / (s32) dacRate;
}
#ifndef VERSION_SH
// put some extra jr $ra's down there please
UNUSED static void filler1(void) {
}

7
lib/src/osAiSetNextBuffer.c
View file

@ -1,6 +1,5 @@
#include "libultra_internal.h"
#include "osAi.h"
#include "hardware.h"
#include "PR/rcp.h"
/**
* It is worth noting that a previous hardware bug has been fixed by a software
@ -33,7 +32,7 @@ s32 osAiSetNextBuffer(void *buff, u32 len) {
return -1;
}
HW_REG(AI_DRAM_ADDR_REG, void *) = (void *) osVirtualToPhysical(bptr);
HW_REG(AI_LEN_REG, u32) = len;
IO_WRITE(AI_DRAM_ADDR_REG, osVirtualToPhysical(bptr));
IO_WRITE(AI_LEN_REG, len);
return 0;
}

48
lib/src/osEPiRawStartDma.c
View file

@ -1,59 +1,39 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
#include "new_func.h"
#include "PR/R4300.h"
// TODO: This define is from piint.h, but including that causes problems...
#define UPDATE_REG(reg, var) \
if (cHandle->var != pihandle->var) \
IO_WRITE(reg, pihandle->var);
#include "piint.h"
// TODO: This define is from os.h, but including that causes problems...
#define PI_DOMAIN1 0
// TODO: These defines are from PR/rcp.h, but including that causes problems...
#define IO_WRITE(addr, data) (*(vu32 *) PHYS_TO_K1(addr) = (u32)(data))
#ifdef VERSION_SH
extern OSPiHandle *__osCurrentHandle[2];
#endif
s32 osEPiRawStartDma(OSPiHandle *pihandle, s32 dir, u32 cart_addr, void *dram_addr, u32 size) {
s32 osEPiRawStartDma(OSPiHandle *pihandle, s32 dir, u32 devAddr, void *dram_addr, u32 size) {
#ifdef VERSION_SH
u32 status;
u32 domain;
#else
register int status;
register u32 status;
#endif
status = HW_REG(PI_STATUS_REG, u32);
while (status & PI_STATUS_ERROR) {
status = HW_REG(PI_STATUS_REG, u32);
}
#ifdef VERSION_SH // TODO: This is the EPI_SYNC macro
domain = pihandle->domain;
if (__osCurrentHandle[domain] != pihandle) {
OSPiHandle *cHandle = __osCurrentHandle[domain];
if (domain == PI_DOMAIN1) {
UPDATE_REG(PI_BSD_DOM1_LAT_REG, latency);
UPDATE_REG(PI_BSD_DOM1_PGS_REG, pageSize);
UPDATE_REG(PI_BSD_DOM1_RLS_REG, relDuration);
UPDATE_REG(PI_BSD_DOM1_PWD_REG, pulse);
} else {
UPDATE_REG(PI_BSD_DOM2_LAT_REG, latency);
UPDATE_REG(PI_BSD_DOM2_PGS_REG, pageSize);
UPDATE_REG(PI_BSD_DOM2_RLS_REG, relDuration);
UPDATE_REG(PI_BSD_DOM2_PWD_REG, pulse);
}
__osCurrentHandle[domain] = pihandle;
}
#ifdef VERSION_SH
EPI_SYNC(pihandle, status, domain);
#else
WAIT_ON_IO_BUSY(status);
#endif
HW_REG(PI_DRAM_ADDR_REG, void *) = (void *) osVirtualToPhysical(dram_addr);
HW_REG(PI_CART_ADDR_REG, void *) = (void *) (((uintptr_t) pihandle->baseAddress | cart_addr) & 0x1fffffff);
IO_WRITE(PI_DRAM_ADDR_REG, osVirtualToPhysical(dram_addr));
IO_WRITE(PI_CART_ADDR_REG, K1_TO_PHYS(pihandle->baseAddress | devAddr));
switch (dir) {
case OS_READ:
HW_REG(PI_WR_LEN_REG, u32) = size - 1;
IO_WRITE(PI_WR_LEN_REG, size - 1);
break;
case OS_WRITE:
HW_REG(PI_RD_LEN_REG, u32) = size - 1;
IO_WRITE(PI_RD_LEN_REG, size - 1);
break;
default:
return -1;

99
lib/src/osInitialize.c
View file

@ -1,26 +1,27 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/R4300.h"
#include "piint.h"
#include "PR/rcp.h"
#include <macros.h>
#define PIF_ADDR_START (void *) 0x1FC007FC
typedef struct {
u32 instr00;
u32 instr01;
u32 instr02;
u32 instr03;
} exceptionPreamble;
u32 inst1;
u32 inst2;
u32 inst3;
u32 inst4;
} __osExceptionVector;
extern __osExceptionVector __osExceptionPreamble;
#if defined(VERSION_EU) || defined(VERSION_SH)
extern u32 __osSetHWintrRoutine(OSHWIntr, s32 (*));
extern void D_802F4380();
extern s32 __osLeoInterrupt(void);
#endif
u32 D_80365CD0; // maybe initialized?
u64 osClockRate = 62500000;
u32 __osFinalrom; // maybe initialized?
u64 osClockRate = OS_CLOCK_RATE;
#ifdef VERSION_SH
u32 osViClock = 0x02E6D354;
u32 osViClock = VI_NTSC_CLOCK;
#endif
u32 D_80334808 = 0; // used in __osException
@ -30,72 +31,64 @@ u32 EU_D_80336C40;
u32 EU_D_80336C44;
u32 __OSGlobalIntMask = OS_IM_ALL;
u32 EU_D_80302090 = 0;
u32 osDDActive = 0;
u8 EU_unusedZeroes[8] = { 0 };
#endif
#define EXCEPTION_TLB_MISS 0x80000000
#define EXCEPTION_XTLB_MISS 0x80000080
#define EXCEPTION_CACHE_ERROR 0x80000100
#define EXCEPTION_GENERAL 0x80000180
extern u32 osResetType;
extern exceptionPreamble __osExceptionPreamble;
void osInitialize(void) {
u32 sp34;
u32 sp30 = 0;
u32 pifdata;
u32 clock = 0;
#if defined(VERSION_EU)
UNUSED u32 eu_sp34;
UNUSED u32 eu_sp30;
u32 leoStatus;
u32 status;
#endif
UNUSED u32 sp2c;
D_80365CD0 = TRUE;
__osSetSR(__osGetSR() | 0x20000000);
__osSetFpcCsr(0x01000800);
while (__osSiRawReadIo(PIF_ADDR_START, &sp34)) {
__osFinalrom = TRUE;
__osSetSR(__osGetSR() | SR_CU1);
__osSetFpcCsr(FPCSR_FS | FPCSR_EV);
while (__osSiRawReadIo(PIF_RAM_END - 3, &pifdata)) {
;
}
while (__osSiRawWriteIo(PIF_ADDR_START, sp34 | 8)) {
while (__osSiRawWriteIo(PIF_RAM_END - 3, pifdata | 8)) {
;
}
*(exceptionPreamble *) EXCEPTION_TLB_MISS = __osExceptionPreamble;
*(exceptionPreamble *) EXCEPTION_XTLB_MISS = __osExceptionPreamble;
*(exceptionPreamble *) EXCEPTION_CACHE_ERROR = __osExceptionPreamble;
*(exceptionPreamble *) EXCEPTION_GENERAL = __osExceptionPreamble;
osWritebackDCache((void *) 0x80000000,
EXCEPTION_GENERAL + sizeof(exceptionPreamble) - EXCEPTION_TLB_MISS);
osInvalICache((void *) 0x80000000,
EXCEPTION_GENERAL + sizeof(exceptionPreamble) - EXCEPTION_TLB_MISS);
*(__osExceptionVector *) UT_VEC = __osExceptionPreamble;
*(__osExceptionVector *) XUT_VEC = __osExceptionPreamble;
*(__osExceptionVector *) ECC_VEC = __osExceptionPreamble;
*(__osExceptionVector *) E_VEC = __osExceptionPreamble;
osWritebackDCache((void *) UT_VEC, E_VEC - UT_VEC + sizeof(__osExceptionVector));
osInvalICache((void *) UT_VEC, E_VEC - UT_VEC + sizeof(__osExceptionVector));
osMapTLBRdb();
osPiRawReadIo(4, &sp30);
sp30 &= ~0xf;
if (sp30) {
osClockRate = sp30;
osPiRawReadIo(4, &clock);
clock &= ~0xf;
if (clock) {
osClockRate = clock;
}
osClockRate = osClockRate * 3 / 4;
if (osResetType == RESET_TYPE_COLD_RESET) {
bzero(osAppNmiBuffer, sizeof(osAppNmiBuffer));
}
#if defined(VERSION_SH)
if (osTvType == TV_TYPE_PAL) {
osViClock = 0x02F5B2D2;
osViClock = VI_PAL_CLOCK;
} else if (osTvType == TV_TYPE_MPAL) {
osViClock = 0x02E6025C;
osViClock = VI_MPAL_CLOCK;
} else {
osViClock = 0x02E6D354;
osViClock = VI_NTSC_CLOCK;
}
#elif defined(VERSION_EU)
eu_sp30 = HW_REG(PI_STATUS_REG, u32);
while (eu_sp30 & PI_STATUS_ERROR) {
eu_sp30 = HW_REG(PI_STATUS_REG, u32);
};
if (!((eu_sp34 = HW_REG(ASIC_STATUS, u32)) & _64DD_PRESENT_MASK)) {
EU_D_80302090 = 1;
__osSetHWIntrRoutine(1, D_802F4380);
WAIT_ON_IO_BUSY(status);
if (!((leoStatus = IO_READ(LEO_STATUS)) & LEO_STATUS_PRESENCE_MASK)) {
osDDActive = 1;
__osSetHWIntrRoutine(1, __osLeoInterrupt);
} else {
EU_D_80302090 = 0;
osDDActive = 0;
}
#endif
}

27
lib/src/osLeoDiskInit.c
View file

@ -1,18 +1,15 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
#include "PR/os.h"
// this file must include some globally referenced data because it is not called anywhere
// data, comes shortly before _Ldtob I think, before crash_screen
extern OSPiHandle *__osPiTable;
// bss
OSPiHandle LeoDiskHandle;
OSPiHandle *__osDiskHandle;
OSPiHandle *osLeoDiskInit(void) {
s32 sp1c;
LeoDiskHandle.type = 2;
LeoDiskHandle.baseAddress = (0xa0000000 | 0x05000000);
s32 saveMask;
LeoDiskHandle.type = DEVICE_TYPE_64DD;
LeoDiskHandle.baseAddress = PHYS_TO_K1(PI_DOM2_ADDR1);
LeoDiskHandle.latency = 3;
LeoDiskHandle.pulse = 6;
LeoDiskHandle.pageSize = 6;
@ -20,15 +17,15 @@ OSPiHandle *osLeoDiskInit(void) {
#ifdef VERSION_SH
LeoDiskHandle.domain = 1;
#endif
HW_REG(PI_BSD_DOM2_LAT_REG, u32) = LeoDiskHandle.latency;
HW_REG(PI_BSD_DOM2_PWD_REG, u32) = LeoDiskHandle.pulse;
HW_REG(PI_BSD_DOM2_PGS_REG, u32) = LeoDiskHandle.pageSize;
HW_REG(PI_BSD_DOM2_RLS_REG, u32) = LeoDiskHandle.relDuration;
IO_WRITE(PI_BSD_DOM2_LAT_REG, LeoDiskHandle.latency);
IO_WRITE(PI_BSD_DOM2_PWD_REG, LeoDiskHandle.pulse);
IO_WRITE(PI_BSD_DOM2_PGS_REG, LeoDiskHandle.pageSize);
IO_WRITE(PI_BSD_DOM2_RLS_REG, LeoDiskHandle.relDuration);
bzero(&LeoDiskHandle.transferInfo, sizeof(__OSTranxInfo));
sp1c = __osDisableInt();
saveMask = __osDisableInt();
LeoDiskHandle.next = __osPiTable;
__osPiTable = &LeoDiskHandle;
__osDiskHandle = &LeoDiskHandle;
__osRestoreInt(sp1c);
__osRestoreInt(saveMask);
return &LeoDiskHandle;
}

15
lib/src/osPiRawReadIo.c
View file

@ -1,14 +1,11 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
#include "piint.h"
extern u32 osRomBase;
s32 osPiRawReadIo(u32 devAddr, u32 *data) {
register u32 status;
s32 osPiRawReadIo(u32 a0, u32 *a1) {
register int status;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY | PI_STATUS_ERROR)) {
status = HW_REG(PI_STATUS_REG, u32);
}
*a1 = HW_REG(osRomBase | a0, u32);
WAIT_ON_IO_BUSY(status);
*data = IO_READ(osRomBase | devAddr);
return 0;
}

53
lib/src/osPiRawStartDma.c
View file

@ -1,56 +1,25 @@
#include "libultra_internal.h"
#include "hardware.h"
extern u32 osRomBase; // TODO: figure out why this is like this
#include "PR/rcp.h"
#include "piint.h"
s32 osPiRawStartDma(s32 dir, u32 cart_addr, void *dram_addr, size_t size) {
register int status;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY | PI_STATUS_ERROR)) {
status = HW_REG(PI_STATUS_REG, u32);
}
register u32 status;
HW_REG(PI_DRAM_ADDR_REG, void *) = (void *) osVirtualToPhysical(dram_addr);
WAIT_ON_IO_BUSY(status);
HW_REG(PI_CART_ADDR_REG, void *) = (void *) (((uintptr_t) osRomBase | cart_addr) & 0x1fffffff);
IO_WRITE(PI_DRAM_ADDR_REG, osVirtualToPhysical(dram_addr));
IO_WRITE(PI_CART_ADDR_REG, K1_TO_PHYS((uintptr_t) osRomBase | cart_addr));
switch (dir) {
case 0:
HW_REG(PI_WR_LEN_REG, u32) = size - 1;
case OS_READ:
IO_WRITE(PI_WR_LEN_REG, size - 1);
break;
case 1:
HW_REG(PI_RD_LEN_REG, u32) = size - 1;
case OS_WRITE:
IO_WRITE(PI_RD_LEN_REG, size - 1);
break;
default:
return -1;
break;
}
return 0;
}
#ifdef VERSION_EU
/*s32 osPiRawStartDma_2(s32 dir, u32 cart_addr, void *dram_addr, size_t size) {
register int status;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY | PI_STATUS_ERROR)) {
status = HW_REG(PI_STATUS_REG, u32);
}
HW_REG(PI_DRAM_ADDR_REG, void *) = (void *) osVirtualToPhysical(dram_addr);
HW_REG(PI_CART_ADDR_REG, void *) = (void *) (((uintptr_t) osRomBase | cart_addr) & 0x1fffffff);
switch (dir) {
case 0:
HW_REG(PI_WR_LEN_REG, u32) = size - 1;
break;
case 1:
HW_REG(PI_RD_LEN_REG, u32) = size - 1;
break;
default:
return -1;
break;
}
return 0;
}*/
#endif

4
lib/src/osSpTaskLoadGo.c
View file

@ -1,5 +1,5 @@
#include "libultra_internal.h"
#include "hardware.h"
#include "PR/rcp.h"
#include <macros.h>
#define _osVirtualToPhysical(ptr) \
@ -31,7 +31,7 @@ void osSpTaskLoad(OSTask *task) {
task->t.flags &= ~M_TASK_FLAG0;
#ifdef VERSION_SH
if (physicalTask->t.flags & M_TASK_FLAG2) {
physicalTask->t.ucode = (u64*)HW_REG((uintptr_t)task->t.yield_data_ptr + 0xBFC, u64*);
physicalTask->t.ucode = (u64 *) IO_READ((uintptr_t)task->t.yield_data_ptr + 0xBFC);
}
#endif
}

13
lib/src/piint.h
View file

@ -110,18 +110,27 @@ OSMesgQueue *osPiGetCmdQueue(void);
#define OS_RAMROM_STACKSIZE 1024
#define WAIT_ON_IOBUSY(stat) \
#define WAIT_ON_IO_BUSY(stat) \
stat = IO_READ(PI_STATUS_REG); \
while (stat & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)) \
stat = IO_READ(PI_STATUS_REG);
#ifdef VERSION_EU
#define WAIT_ON_LEO_IO_BUSY(stat) \
stat = IO_READ(PI_STATUS_REG); \
while (stat & PI_STATUS_IO_BUSY) \
stat = IO_READ(PI_STATUS_REG);
#else
#define WAIT_ON_LEO_IO_BUSY WAIT_ON_IO_BUSY
#endif
#define UPDATE_REG(reg, var) \
if (cHandle->var != pihandle->var) \
IO_WRITE(reg, pihandle->var);
#define EPI_SYNC(pihandle, stat, domain) \
\
WAIT_ON_IOBUSY(stat) \
WAIT_ON_IO_BUSY(stat) \
\
domain = pihandle->domain; \
if (__osCurrentHandle[domain] != pihandle) \

2
sm64.ld
View file

@ -272,7 +272,9 @@ SECTIONS
BUILD_DIR/libultra.a:osMapTLBRdb.o(.text);
BUILD_DIR/libultra.a:osPiRawReadIo.o(.text);
BUILD_DIR/libultra.a:__osSetHWintrRoutine.o(.text);
#ifdef VERSION_EU
BUILD_DIR/libultra.a:D_802F4380.o(.text);
#endif
BUILD_DIR/libultra.a:func_802F4A20.o(.text);
BUILD_DIR/libultra.a:osTimer.o(.text);
#ifdef VERSION_EU

1
undefined_syms.txt
View file

@ -1,7 +1,6 @@
/* libultra OS symbols */
/* boot and osException symbols */
/* most of these should be in hardware.h */
/* exceptions */